Datasheet
Datasheet
SN54HC595, SN74HC595 SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 SNx4HC595 8-Bit Shift Registers With 3-State Output Registers 1 Features 3 Description • • • The SNx4HC595 devices contain an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. • • • • • • 8-bit serial-in, parallel-out shift Wide operating voltage range of 2 V to 6 V High-current 3-state outputs can drive up to 15 LSTTL loads Low power consumption: 80-μA (maximum) ICC tpd = 13 ns (typical) ±6-mA output drive at 5 V Low input current: 1 μA (maximum) Shift register has direct clear On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. Device Information PART NUMBER 2 Applications • • • • Network switches Power infrastructure LED displays Servers OE SRCLR SRCLK SER (1) BODY SIZE (NOM) SN54HC595FK LCCC (20) 8.89 mm × 8.89 mm SN54HC595J CDIP (16) 21.34 mm × 6.92 mm SN74HC595N PDIP (16) 19.31 mm × 6.35 mm SN74HC595D SOIC (16) 9.90 mm × 3.90 mm SN74HC595DW SOIC (16) 10.30 mm × 7.50 mm SN74HC595DB SSOP (16) 6.20 mm × 5.30 mm SN74HC595PW TSSOP (16) 5.00 mm × 4.40 mm (1) RCLK PACKAGE For all available packages, see the orderable addendum at the end of the data sheet. 13 12 10 11 14 1D C1 R 3R C3 3S 15 2S 2R C2 R 3R C3 3S 1 2S 2R C2 R 3R C3 3S 2 2S 2R C2 R 3R C3 3S 3 2S 2R C2 R 3R C3 3S 4 2S 2R C2 R 3R C3 3S 5 2S 2R C2 R 3R C3 3S 6 2S 2R C2 R 3R C3 3S 7 QA QB QC 9 QD QE QF QG QH QH′ Pin numbers shown are for the D, DB, DW, J, N, NS, PW, and W packages. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................5 6.5 Electrical Characteristics.............................................5 6.6 Timing Requirements.................................................. 6 6.7 Switching Characteristics............................................8 6.8 Operating Characteristics........................................... 8 6.9 Typical Characteristics................................................ 9 7 Parameter Measurement Information.......................... 10 8 Detailed Description...................................................... 11 8.1 Overview................................................................... 11 8.2 Functional Block Diagram......................................... 11 8.3 Feature Description...................................................12 8.4 Device Functional Modes..........................................12 9 Application and Implementation.................................. 13 9.1 Application Information............................................. 13 9.2 Typical Application.................................................... 13 10 Power Supply Recommendations..............................15 11 Layout........................................................................... 15 11.1 Layout Guidelines................................................... 15 11.2 Layout Example...................................................... 15 12 Device and Documentation Support..........................16 12.1 Documentation Support.......................................... 16 12.2 Support Resources................................................. 16 12.3 Trademarks............................................................. 16 12.4 Electrostatic Discharge Caution..............................16 12.5 Glossary..................................................................16 13 Mechanical, Packaging, and Orderable Information.................................................................... 16 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (November 2009) to Revision I (August 2015) Page • Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1 • Deleted Ordering Information table. ...................................................................................................................1 • Added Military Disclaimer to Features list...........................................................................................................1 Changes from Revision I (August 2015) to Revision J (October 2021) Page • Updated the device information table, ESD ratings table, and the device functional modes table to fit modern data sheet standards.......................................................................................................................................... 1 2 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 5 Pin Configuration and Functions D, N, NS, J, DB, or PW Package 16-Pin SOIC, PDIP, SO, CDIP, SSOP, or TSSOP Top View FK Package 20-Pin LCCC Top View Table 5-1. Pin Functions PIN NAME SOIC, PDIP, SO, CDIP, SSOP, or TSSOP LCCC GND 8 10 OE 13 QA 15 QB QC I/O(1) DESCRIPTION — Ground Pin 17 I Output Enable 19 O QA Output 1 2 O QB Output 2 3 O QC Output QD 3 4 O QD Output QE 4 5 O QE Output QF 5 7 O QF Output QG 6 8 O QG Output QH 7 9 O QH Output QH' 9 12 O QH' Output RCLK 12 14 I RCLK Input SER 14 18 I SER Input SRCLK 11 14 I SRCLK Input SRCLR 10 13 I SRCLR Input — No Connection — Power Pin 1 NC — 16 11 16 VCC (1) — 20 Signal Types: I = Input, O = Output, I/O = Input or Output. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 3 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) VCC (1) MIN MAX UNIT –0.5 7 V VI < 0 or VI > VCC ±20 mA VO < 0 or VO > VCC ±20 mA VO = 0 to VCC ±35 mA ±70 mA 150 °C 150 °C Supply voltage (2) IIK Input clamp current IOK Output clamp current IO Continuous output current (2) Continuous current through VCC or GND TJ Junction temperature Tstg Storage temperature (1) (2) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) 1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted)(1) SN54HC595 VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage SN74HC595 MIN NOM MAX MIN NOM MAX 2 5 6 2 5 6 VCC = 2 V 1.5 1.5 VCC = 4.5 V 3.15 3.15 VCC = 6 V 4.2 UNIT V V 4.2 VCC = 2 V 0.5 0.5 VCC = 4.5 V 1.35 1.35 VCC = 6 V 1.8 1.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V Δt/Δv Input transition rise or fall time(2) TA Operating free-air temperature VCC = 2 V 1000 1000 VCC = 4.5 V 500 500 VCC = 6 V (1) 400 –55 125 ns 400 –40 85 °C (2) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004. If this device is used in the threshold region (from VILmax = 0.5 V to VIH min = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 6.4 Thermal Information SN74HC595 THERMAL METRIC(1) RθJA (1) D (SOIC) DB (SSOP) DW (SOIC) N (PDIP) NS (SO) PW (TSSOP) 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 73 82 57 67 64 108 Junction-to-ambient thermal resistance UNIT °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –20 μA VOH VI = VIH or VIL QH′, IOH = –4 mA QA – QH, IOH = –6 mA QH′, IOH = −5.2 mA QA – QH, IOH = –7.8 mA IOL = 20 μA VOL VI = VIH or VIL QH′, IOL = 4 mA QA – QH, IOL = 6 mA QH′, IOL = 5.2 mA QA – QH, IOL = 7.8 mA VCC TA = 25°C MIN TYP MAX SN54HC595 SN74HC595 MIN MIN MAX 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 3.98 4.3 3.7 3.84 3.98 4.3 3.7 3.84 5.48 5.8 5.2 5.34 5.48 5.8 5.2 4.5 V 6V MAX V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 0.17 0.26 0.4 0.33 0.15 0.26 0.4 0.33 0.15 0.26 0.4 0.33 4.5 V 6V UNIT V II VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA IOZ VO = VCC or 0, QA – QH 6V ±0.01 ±0.5 ±10 ±5 µA ICC VI = VCC or 0, IO = 0 8 160 80 µA 10 10 10 pF Ci 6V 2 V to 6V 3 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 5 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 6.6 Timing Requirements over operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency SRCLK or RCLK high or low tw Pulse duration SRCLR low SER before SRCLK↑ SRCLK↑ before RCLK↑(1) tsu Set-up time SRCLR low before RCLK↑ SRCLR high (inactive) before SRCLK↑ th Hold time, SER after SRCLK↑ TA = 25°C SN54HC595 MIN MIN MAX MAX SN74HC595 MIN MAX 2V 6 4.2 5 4.5 V 31 21 25 6V 36 25 29 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 75 113 94 4.5 V 15 23 19 6V 13 19 16 2V 50 75 65 4.5 V 10 15 13 6V 9 13 11 2V 50 75 60 4.5 V 10 15 12 6V 9 13 11 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 UNIT MHz ns ns ns (1) This set-up time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 SRCLK SER RCLK SRCLR OE QA QB QC QD QE QF QG QH QH’ NOTE: implies that the output is in 3-State mode. Figure 6-1. Timing Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 7 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 6.7 Switching Characteristics Over recommended operating free-air temperature range. PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE fmax 50 pF SRCLK QH′ 50 pF tpd RCLK tPHL SRCLR ten OE tdis OE QA – QH 50 pF QH′ 50 pF QA – QH 50 pF QA – QH 50 pF QA – QH 50 pF tt QH′ tpd RCLK ten OE tt 50 pF QA – QH 150 pf QA – QH 150 pf QA – QH 150 pf VCC TA = 25°C SN54HC595 MAX MIN MAX SN74HC595 MIN TYP MIN 2V 6 26 4.2 5 4.5 V 31 38 21 25 6V 36 42 25 29 MAX UNIT MHz 2V 50 160 240 200 4.5 V 17 32 48 40 6V 14 27 41 34 2V 50 150 225 187 4.5 V 17 30 45 37 6V 14 26 38 32 2V 51 175 261 219 4.5 V 18 35 52 44 6V 15 30 44 37 2V 40 150 255 187 4.5 V 15 30 45 37 6V 13 26 38 32 2V 42 200 300 250 4.5 V 23 40 60 50 6V 20 34 51 43 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 2V 28 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 2V 60 200 300 250 4.5 V 22 40 60 50 6V 19 34 51 43 2V 70 200 298 250 4.5 V 23 40 60 50 6V 19 34 51 43 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 ns ns ns ns ns ns ns ns 6.8 Operating Characteristics TA = 25°C PARAMETER Cpd 8 Power dissipation capacitance TEST CONDITIONS TYP UNIT No load 400 pF Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 6.9 Typical Characteristics 40 OUTPUTS = µ+,¶ OE = µ/2:¶ 35 30 25 20 ICC(nA) 15 10 5 0 -5 0 1 2 3 VCC(V) 4 5 6 Figure 6-2. SN74HC595 ICC vs. VCC Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 9 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 7 Parameter Measurement Information VCC S1 Test Point From Output Under Test tPZH ten RL CL (see Note A) RL CL S1 S2 50 pF or 150 pF Open Closed 1 kΩ Closed Open PARAMETER tPZL tPHZ tdis S2 tPLZ 1 kΩ LOAD CIRCUIT Reference Input VCC 50% Data Input VCC 50% 10% 50% VCC 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% 50% 10% tf 90% VCC 50% 10% 0 V tf Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL VOH 50% 10% V OL tf tPLZ Output Waveform 1 (See Note B) 90% tr VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES ≈VCC ≈VCC 50% 10% tPZH tPLH 50% 10% 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% tPLH VCC tr VOLTAGE WAVEFORMS PULSE DURATIONS 50% Open 0V 0V Input Open th tsu 0V 50% Open 50% 50% tw Low-Level Pulse Closed 50 pF or 150 pF tpd or tt High-Level Pulse Open Closed 50 pF VOL tPHZ Output Waveform 2 (See Note B) 50% 90% VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. t PLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 7-1. Load Circuit and Voltage Waveforms 10 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 8 Detailed Description 8.1 Overview The SNx4HC595 is part of the HC family of logic devices intended for CMOS applications. The SNx4HC595 is an 8-bit shift register that feeds an 8-bit D-type storage register. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. 8.2 Functional Block Diagram OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D C1 R 3R C3 3S 15 2S 2R C2 R 3R C3 3S 1 2S 2R C2 R 3R C3 3S 2 2S 2R C2 R 3R C3 3S 3 2S 2R C2 R 3R C3 3S 4 2S 2R C2 R 3R C3 3S 5 2S 2R C2 R 3R C3 3S 6 2S 2R C2 R 3R C3 3S 7 QA QB QC 9 QD QE QF QG QH QH′ Pin numbers shown are for the D, DB, DW, J, N, NS, PW, and W packages. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 11 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 8.3 Feature Description The SNx4HC595 devices are 8-bit Serial-In, Parallel-Out Shift Registers. They have a wide operating current of 2 V to 6 V, and the high-current 3-state outputs can drive up to 15 LSTTL Loads. The devices have a low power consumption of 80-μA (Maximum) ICC. Additionally, the devices have a low input current of 1 μA (Maximum) and a ±6-mA Output Drive at 5 V. 8.4 Device Functional Modes Table 8-1 lists the functional modes of the SNx4HC595 devices. Table 8-1. Function Table INPUTS SER 12 SRCLK SRCLR FUNCTION RCLK OE H Outputs QA – QH are disabled. X X X X X X X X L Outputs QA – QH are enabled. X X L X X Shift register is cleared. L ↑ H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X X X ↑ X Shift-register data is stored in the storage register. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The SNx4HC595 is a low-drive CMOS device that can be used for a multitude of bus interface type applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on the outputs. 9.2 Typical Application SRCLR SRCLK 5 RCLK Controller OE SER 10 15 11 1 12 2 13 3 14 4 5 QA 560 QB 560 QC QD QE QF 6 QG 7 QH 9 Q+¶ 560 560 560 560 560 560 +5V VCC 16 8 GND 0.1 F Figure 9-1. Typical Application Schematic 9.2.1 Design Requirements This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load conditions should be considered to prevent ringing. Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 13 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 9.2.2 Detailed Design Procedure • • Recommended input conditions – Specified high and low levels. See (VIH and VIL) in Section 6.3 table. – Specified high and low levels. See (VIH and VIL) in Section 6.3 table. – Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC Recommend output conditions – Load currents should not exceed 35 mA per output and 70 mA total for the part – Outputs should not be pulled above VCC 9.2.3 Application Curves 60 50 40 30 tpd(ns) 20 10 0 0 2 4 VCC(V) 6 8 Figure 9-2. SN75HC595 tpd vs. VCC 14 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in Section 6.3 table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a 1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple-bit logic devices, inputs should never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Figure 11-1 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled. 11.2 Layout Example Vcc Unused Input Input Output Unused Input Output Input Figure 11-1. Layout Diagram Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 15 SN54HC595, SN74HC595 www.ti.com SCLS041J – DECEMBER 1982 – REVISED OCTOBER 2021 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation, see the following: • Texas Instruments, Implications of Slow or Floating CMOS Inputs application brief 12.2 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.3 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.5 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. 16 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: SN54HC595 SN74HC595 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2026 PACKAGING INFORMATION Orderable part number Status Material type (1) (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material MSL rating/ Peak reflow (4) (5) Op temp (°C) Part marking (6) 5962-86816012A NRND Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 596286816012A SNJ54HC 595FK 5962-8681601EA Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8681601EA SNJ54HC595J 5962-8681601VEA Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8681601VE A SNV54HC595J 5962-8681601VEA.A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8681601VE A SNV54HC595J 5962-8681601VFA Active Production CFP (W) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8681601VF A SNV54HC595W 5962-8681601VFA.A Active Production CFP (W) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8681601VF A SNV54HC595W SN54HC595J NRND Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54HC595J SN54HC595J.A NRND Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 SN54HC595J SN74HC595DBR Active Production SSOP (DB) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595DBR.A Active Production SSOP (DB) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595DBRE4 Active Production SSOP (DB) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595DBRG4 Active Production SSOP (DB) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595DR Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595DR.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595DRE4 Active Production null (null) | 2500 | LARGE T&R - Call TI Call TI -40 to 85 SN74HC595DRG3 Active Production SOIC (D) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595DRG3.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595DRG4 Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595DRG4.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595DT Obsolete Production SOIC (D) | 16 - - Call TI Call TI -40 to 85 HC595 Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com Orderable part number (1) 18-Sep-2026 Status Material type (1) (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material MSL rating/ Peak reflow (4) (5) Op temp (°C) Part marking (6) SN74HC595DW Obsolete Production SOIC (DW) | 16 - - Call TI Call TI -40 to 85 SN74HC595DWR Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 SN74HC595DWR.A Active Production SOIC (DW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 HC595 SN74HC595N Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74HC595N SN74HC595N.A Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74HC595N SN74HC595NE4 Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -40 to 85 SN74HC595N SN74HC595NSR Active Production SOP (NS) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595NSR.A Active Production SOP (NS) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595PW Obsolete Production TSSOP (PW) | 16 - - Call TI Call TI -40 to 85 HC595 SN74HC595PWR Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595PWR.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595PWRG4 Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SN74HC595PWRG4.A Active Production TSSOP (PW) | 16 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HC595 SNJ54HC595FK NRND Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 596286816012A SNJ54HC 595FK SNJ54HC595FK.A NRND Production LCCC (FK) | 20 55 | TUBE No SNPB N/A for Pkg Type -55 to 125 596286816012A SNJ54HC 595FK SNJ54HC595J Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8681601EA SNJ54HC595J SNJ54HC595J.A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 5962-8681601EA SNJ54HC595J Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2026 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC595, SN54HC595-SP, SN74HC595 : • Catalog : SN74HC595, SN54HC595 • Enhanced Product : SN74HC595-EP, SN74HC595-EP • Military : SN54HC595 • Space : SN54HC595-SP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2026 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS K0 P1 B0 W Reel Diameter Cavity A0 B0 K0 W P1 A0 Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC595DBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1 SN74HC595DR SOIC D 16 2500 330.0 SN74HC595DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC595DRG3 SOIC D 16 2500 SN74HC595DRG4 SOIC D 16 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1 330.0 16.4 6.5 10.3 2.1 8.0 16.0 SN74HC595DRG4 SOIC D 16 Q1 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC595DWR SOIC DW SN74HC595NSR SOP NS 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 16 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 SN74HC595NSR SOP Q1 NS 16 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1 SN74HC595PWR SN74HC595PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC595PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.3 1.6 8.0 12.0 Q1 SN74HC595PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.3 1.6 8.0 12.0 Q1 SN74HC595PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W L H *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC595DBR SSOP DB 16 2000 353.0 353.0 32.0 SN74HC595DR SOIC D 16 2500 340.5 336.1 32.0 SN74HC595DR SOIC D 16 2500 340.5 336.1 32.0 SN74HC595DRG3 SOIC D 16 2500 366.0 364.0 50.0 SN74HC595DRG4 SOIC D 16 2500 353.0 353.0 32.0 SN74HC595DRG4 SOIC D 16 2500 340.5 336.1 32.0 SN74HC595DWR SOIC DW 16 2000 350.0 350.0 43.0 SN74HC595NSR SOP NS 16 2000 353.0 353.0 32.0 SN74HC595NSR SOP NS 16 2000 353.0 353.0 32.0 SN74HC595PWR TSSOP PW 16 2000 353.0 353.0 32.0 SN74HC595PWR TSSOP PW 16 2000 356.0 356.0 35.0 SN74HC595PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC595PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0 SN74HC595PWRG4 TSSOP PW 16 2000 353.0 353.0 32.0 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2026 TUBE T - Tube height L - Tube length W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) 5962-86816012A FK LCCC 20 55 506.98 12.06 2030 NA 5962-8681601EA J CDIP 16 25 506.98 15.24 13440 NA 5962-8681601VEA J CDIP 16 25 506.98 15.24 13440 NA 5962-8681601VEA.A J CDIP 16 25 506.98 15.24 13440 NA 5962-8681601VFA W CFP 16 25 506.98 26.16 6220 NA 5962-8681601VFA.A W CFP 16 25 506.98 26.16 6220 NA SN74HC595N N PDIP 16 25 506 13.97 11230 4.32 SN74HC595N N PDIP 16 25 506 13.97 11230 4.32 SN74HC595N.A N PDIP 16 25 506 13.97 11230 4.32 SN74HC595N.A N PDIP 16 25 506 13.97 11230 4.32 SN74HC595NE4 N PDIP 16 25 506 13.97 11230 4.32 SN74HC595NE4 N PDIP 16 25 506 13.97 11230 4.32 SNJ54HC595FK FK LCCC 20 55 506.98 12.06 2030 NA SNJ54HC595FK.A FK LCCC 20 55 506.98 12.06 2030 NA SNJ54HC595J J CDIP 16 25 506.98 15.24 13440 NA SNJ54HC595J.A J CDIP 16 25 506.98 15.24 13440 NA Pack Materials-Page 3 PACKAGE OUTLINE DB0016A SSOP - 2 mm max height SCALE 1.500 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 14X 0.65 16 1 2X 6.5 5.9 NOTE 3 4.55 8 9 16X B 5.6 5.0 NOTE 4 0.38 0.22 0.1 C A B 0.25 0.09 SEE DETAIL A 2 MAX 0.25 GAGE PLANE 0 -8 0.95 0.55 0.05 MIN DETAIL A A 15 TYPICAL 4220763/A 05/2022 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-150. www.ti.com EXAMPLE BOARD LAYOUT DB0016A SSOP - 2 mm max height SMALL OUTLINE PACKAGE SYMM 16X (1.85) (R0.05) TYP 1 16 16X (0.45) SYMM 14X (0.65) 8 9 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK OPENING SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) 0.05 MIN ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS 15.000 4220763/A 05/2022 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DB0016A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 16X (1.85) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220763/A 05/2022 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board as