Datasheet

Synertek SY1402A/1403A/1404A 1024-Bit Dynamic Shift Registers

Second-source datasheet for the 1404A-type MOS shift registers used as the KENBAK-1's memory.

Author: Synertek
Type: Datasheet
Credit: Synertek; copy from bitsavers.mirrorservice.org

~ 1024-Bit Dynamic ~ Shift Registers ~ Quad, Dual, Single SY1402A, SY1403A, SY1404A MEMORY PRODUCTS Slrnertek: • INCORPORATED o Synertek ion implanted silicon gate process • • 5 MHz data rate-minimum o Reduced clock capacitance, 85 pF • 2.5 MHz clock rate • The SY1402A, 1403A and 1404A 2</> dynamic shift registers utilize 1/0 multiplexing techniques to attain a 5.0 MHz data rate with a clock rate of only 2.5 MHz. The inputs and outputs are bipolar and MOS compatible for ease of implementation in a TTL, DTL and a high- or low-threshold MOS system. The SY1402A, 1403A and 1404A are used effectively in applications requiring low cost serial memory such as CRT refresh, line and page storage for facsimile transmitters and receivers, and character stpfage· for high speed printers. OUTPUT 1 IN 4 NC NC IN 1 OUT4 ¢ 1 NC Vee Voo OUT2 ¢2 NC IN 3 SVM1403A IN 2 OUT 3 8 Vee IN 2 2 7 ¢1 3 4 6 5 PIN CONFIGURATION Vee SVM1404A 1• Voo PIN CONFIGURATION Vee OUT2 ¢2 Reduced power dissipation, 80 µW/bit at 1.0 MHz silicon gate design. These savings directly affect the cost of the overhead circuitry (clock drivers, power supplies) for a shift register memory system. Clock power and Voo current have been significantly reduced due to the advantages inherent in an ion implanted silicon gate design over a conventional PIN CONFIGURATION TTL, DTL compatible SVP1402A SVC1402A IN 1 OUT 1 8 1• 92 2 NC 3 6 ¢1 Voo 4 5 IN NC SVP1403A ORDERING INFORMATION SVP1404A Order Number Package Type Organization Temperature Range SYP1404A SYM1404A SYP1403A SYM1403A SYP1402A SYC1402A Plastic Dip TO Can Plastic Dip TO Can Plastic Dip Ceramic Dip 1024 x 1 1024 x 1 512 x 2 512 x 2 256 x 4 256 x 4 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to+ 70°C 0°C to +70°C 0°C to +70°C 2-2 Vee OUT SY1402A,SY1403A,SY1404A ABSOLUTE MAXIMUM RATINGS 1 0°C to 70°C Temperature Under Bias Storage Temperature -65°C to +160°C Power Dissipation (2) 1 Watt Data and Clock Input Voltages and Supply Voltages with +0.5V to -20V respect to Vee D.C. CHARACTERISTICS TA = 0°C to 70°C, Vee = +5V ±5%, unless otherwise specified Voo = -5V ±5% or -9V ±5% Symbol Test Min. Typ.(3) Max. Unit Conditions iu Input Load Current <10 500 nA TA=25°C ILO Output Leakage Current <10 1000 nA VouT = O.OV, TA= 25°C 10 1000 nA M,ilx. VILC· TA= 25°C ILC Clock Leakage Current V1L Input "Low" Voltage Vcc-10 Vcc-4.2 v V1H Input "High" Voltage Vcc-2 Vcc+.3 v 20 mA Voo = -5V ±5% loD1 Power Supply Current 15 loD2 Power Supply Current 22 mA V1LC Clock Input Low Voltage Vcc-17 vcc-15 v V1HC Clock Input High Voltage Vcc-1 Vcc+.3 v 0.5 v Vol Output Low Voltage VoH1 Output High Voltage Driving TTL VOH2 Output High Voltage Driving MOS -.3 TA, 25"C} Tc= 0°C O"'P"' "<log'c "0". 5 MHz Data Rate, 33% Duty Cycle. Continuous Operation, V1Lc = Vcc-17V RL 1 = 3K to VDD· loL = 1.6 mA 2.4 3.5 v Vcc-1.6 Vcc-1 v RL2 = 4.7K to VDD (Seep. 4 for connection) mA TA=25°C] 22 mA Tc= 0°C Vcc-12.6 v RL 1=3K to VDD· loH = -100µA VDD = -9V ±5% IDD3 Power Supply Current 20 15 f Output at Logic "O", 3 MHz Data Rate, 26% Duty Cycle, Continuous Operation, V1LC = Vcc-14.7V 1004 Power Supply Current V1LC Clock Input Low Voltage Vcc-147 V1HC Clock Input High Voltage Vcc-1 Vol Output Low Voltage VOH1 Output High Voltage Driving TTL 2.4 VoH2 Output High Voltage Driving MOS Vcc-1.9 Note 1: Stresses listed under "Absolute Maximum Ratings" may cause permilnent damage to the device This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2: The 1 watt dissipation is not to be construed.as i.ln operating rating (see note 1 ). For operating at elevated temperatures the device must be derated based as shown on page 4. When operating at VDD = -5V±5% the maximum duty cycle is 33% and at VoD = -9V+5% the maximum duty cycle is 26%. In applications the duty cycle should be a minimum to reduce power dissipation. Duty cycle= [t<t>PW + 1/2 ( tR + IF)] x clock rate. Note 3: Typical values are at TA= 25°C and at nominal voltages. Vcc+.3 v RL 1=4.7K to VDO· loL = 1.6 mA 0.5 v RL 1=4.7K to VoD. IOL = 1.6 mA 3.5 v RLJ =4.7K toVoD.loH=-100µA Vcc-1 v RL2 = 6.2K to VDD} RL3=3.9K to Vee -.3 2-3 (Seep. 4 for connection) § SY1402A,SY1403A,SY1404A A.C. CHARACTERISTICS TA = 0°C to 70°C; Vee = +5V ±5% Symbol v00 = -9V ±5% Voo = -5V ±5% (Test Load 1) Test Min. Max. Unit (Test Load 2) Min. Max. 1.5 MHz 5.0 Note 1 3.0 MHz Frequency Clock Rep Rate Frequency Data Rep Rate Note 1 t</>PW Clock Pulse Width .130 10 .170 10 µsec t</>D Clock Pulse Delay 10 Note 1 10 Note 1 nsec tR. tF Clock Pulse Transition 1000 nsec tow Data Write Time (Set Up) 30 toH Data To Clock Hold Time 20 tA+· tA- Clock To Data Out Delay CAPACITANCE 2 Symbol 2.5 1000 nsec 60 nsec 20 90 nsec 110 Vee= +5V ±5%, V 00 = -5V ±5% or -9V ±5%, TA= 25°C Test Typ. Max. Conditions v,N =Vee } C1N Input Capacitance 5 pF 10 pF CouT Output Capacitance 5 pF 10 pF VouT =Vee Cr/> Clock Capacitance 70 pF 85 pF v<t> =Vee c<1>1<1>2 Clock to Clock Capacitance 11 pF 16 pF v<t> =Vee Note 1: See page 4 for guaranteed curve. f = 1 MHz Note 2: This parameter is periodically sampled and is not 100% tested. SWITCHING CHARACTERISTICS Conditions of Test Input rise and fall times 10 nsec Output Load is 1 TTL gate 4.7k V 00 = -5V ± 5% 04 CTOTAL = 10 pF v00 = -9V ± 5% 05 Timing Diagram BIT1 BIT2 ..t11------,-oo-Ya""- _8~ 1 BIT 2 VIHC I ¢1 I 90% 90% -: , ,+ - - - - - - - V1 LC 11 II tF-11-- ~I- tR 06 *tow and toH same for t"., 2 **N 2b6forSY1402A.N=512furSY1403A.N~l024furSY1404A 2-4 SV1402A,SV1403A,SV1404A TYPICAL CHARACTERISTICS 5: )> 10k t----+---+---+-----+--<f----+---10-4 ~ c ~ E ; 400 1----+--+--+---+--+- .._...t---+---+---i 1o-3 () 100 ~ 95 ,_.-~---110-2 ~ ~ 400 o ;:: 5 () w <! c.. c r ~ Vi (f) Ci ~ s: 1k ;: 1o 1----+---+-~""'F---+---j--+---t 10-1 ~ <! 0 m 0 200 1----+--+---+------+--+--+---t---+----< r )> 3': -< 0 c.. O. l i-----+-----+---+---+- VD o = -5 V 0 R v 00 = -9V 10 g ~ 9 10 20 30 40 50 60 70 80 90 0 100 AMBIENT TEMPERATURE (°C) 10 20 25 30 40 50 60 70 AMBIENT TEMPERATURE (°C) 07 MAXIMUM ALLOWABLE POWER DISSIPATION 08 MINIMUM OPERATING DATA RATE OR MAXIMUM CLOCK PULSE DELAY VS. TEMPERATURE DTL/TTL MOS Interfaces Vee I I 3k _ _ _ _V_e_e_ _ _,.. Ruf SY 1402A/3A/4A tc>~--t~---t1IN Vee SY 1402A/3A/4A I OUTt---tt----t1IN DTL/TTL OUT1------~-~ o2 DTL/TTL Voo Voo RL Load Resistor Values for Different V00 Supplies 09 2-5 Vee= 5V Vee= 5V v 00 =-5V v 00 = -9V Rll 30k 4.7k RL2 4.7k 6.2k Ru Not required 3.9k