Manual / Guide · 1971
KENBAK-1 Theory of Operation (1971)
How the KENBAK-1's TTL logic and shift-register memory work, state by state.
Manual / Guide · 1971
How the KENBAK-1's TTL logic and shift-register memory work, state by state.
THEORY OF OPEP~TION INTRODUCTION The reader is assumed to be acquainted with general digital theory for computers. It is also assumed that the reader is familiar with the programming material. He need not be a programmer but he should understand what the individual instructions accomplish. The broad concepts and the detailed schematics of the KENBAK-l computer are given. The material is divided into these sections: Glossary of Signals Block Diagram State Diagram Definition of Circuit Elements Kenbak-l Computer Circuit Schematics The Glossary of Signals is presented first to emphasize that it does exist and that it can be a useful working tool in studying other aspects of the presentation. However, it is a reference section and not a fundamental mode for presenting ideas. The local reference in the Glossary is the schematic page number where that signal originates. -9- GLOSSARY Name Local Reference Definition or Comment A (20) One of the two inputs to the adder/subtractor, see also B. A7 (03) The most significant address bit which selects one of the two delay lines which constitute the memory. B (20) One of the two inputs to the adder/subtractor. During subtraction B is subtracted from A. BD (21) A flipflop used to detect whether any bits Used in the A, B, or X registers are 1. in evaluating JC. BM (23) An AND of the conditions 1. Skip or Set instructions, 2. The bit time (BT) of the selected bit, and 3. State SL. In the state diagram, BM is used in broad sense of 1 to mean Bit Manipulation instructions. BT (18) The bit manipulation instructions designate a specific bit time. BT is true during that time. BU (05) The eight data input switches are scanned by TO through T7 and ORed together to produce the serial signal BU. c (19) The carry flipflop in the adder. CL (04) True when the Clear pushbutton is depressed. elY1 (02) The comparison between the memory address register and the desired address is true. eM is only valid during T7. (01) CR (19) Major system clock pulse. A bit time starts with the negativ~ going transition of CP. Carry to the next bit before being delayed by c. -10- GLOSSARY CT (25) Output of multivibrator. Cy (21) A flipflop which holds the carry from the previous byte. (01) Clock pulse that occurs only during T7. Has same phase as CP. (04) Display Address (from pushbutton of that name). Goes to ground when button is pushed. (04) Display Data (from Read Memory pushbutton) after being cleaned up. Goes to ground when button is pushed. DEX Index address mode. DLO (24) Output of memory delay line O. DLI (24) Output of memory delay line 1. (04) Enter Address (from Set Address pushbutton) after being cleaned up. Goes to ground when button is pushed. ED (22) Automatic processing should End after the current instruction is finished. EN (04) Enter Data (from Store Memory pushbutton) after being cleaned up. Goes to ground when button is pushedo Fl/F2 (Ol) Inputs to delay line clock drivers. GO (04) Signal from Start Pushbutton after being cleaned up. Goes to ground when button is pushed. (04) Signal from Stop Pushbutton. Goes to ground when button is pushed. Immediate or constant address mode. IMr1ED IN IND (04) True during byte time when location 377 (Input) is being read from memory. Indirect address mode. -11- GLOSSARY IO/I? (14) Any Jump instruction. J JC Generally the I register is the instruction register. 17 is the most significant bit and 10 is the least significant bit. As an ·instruction register, I holds the first byte of an instruction. (21) See also JD, JI, JM, JP. Jump Conditions are true; the Jump should be made. A Jump instruction with direct addressing (not indirect). JD JDLO (24) Input to delay line O. JDLI (24 ) Input to delay line 1. JI A Jump instruction with indirect addressing. JM A Jump and Mark instruction. JP A straight Jump instruction (no Mark). JSO/JS4 (10) Inputs to 5 state flipflops. KP (22) This signal is ground if a skip is required in the bit test instructions. KS (06) Shift control to K register. indicates a shift. KO/K7 (07) The K Register controls the data lamps. is the most significant bito LC (02) Carry flipflop for memory address (L) register. When LC is a 1 at T7 the next address is 177 (and 377). (IS) Shift control signal for left shifting. (02) Memory address register. via LO. LOlL? -12- At ground, KS Read serially K7 GLOSSARY Memory address mode. MEM MR (03) Memory read. Is the output of DLO or DLI as selected by A7. OF (19) Overflow as detected by the adder. OV (21) Overflow delayed for one byte time. PF (22) Four is to be added to the P register (Plus Four) . PO (22) One is to be added to the P register (Plus One). PT (22) Two is to be added to the P register (Plus Two). QB (09) State to wait for Start button to be released. QC (09) Idle state for manual operations. QD (09) State to seek address comparison for manual operations. QE (09) State to execute manual operations. QF (09) State to wait for control buttons to be released. (03) Desired address in logic complement form. RR ( 18) Control signal for right shifts and rotates. SA (09 ) State to seek P register. SB (09) State to read and update P register. SC (09) State to seek instruction. SD (09) State to read first byte of instruction. SE (09) State to read second byte of instruction. SF (09) State to seek indirect address. SG (09) State to read indirect address. SH (09) State to seek X register. -13- GLOSSARY SJ (09) State to do index address computation. SK (09) State to seek operand. SL (09 ) State to read operand and execute bit manipulation instructions. S~1 (09 ) State to seek A, B, or X register. SN (09) State to execute change to A, B, or X (also P) register. SP (09) State to load I with A, B, or X register. SQ (09) State to modify P in Jump and Mark instructions. SR (09) State to seek address for storing in memory. 58 (09 ) State to store data in memory. ST (09 ) State to seek P register. SU (09 ) State to seek A or B register. sur1 (19) Output of adder. sv (09 ) State to read A or B register. SW (09) State to perform shift/rotates in W register. SX (09) State to seek A or B register. Sy (09) State to store W register in A or B register. SZ (09) State to evaluate jump conditions. SO/85 (09 ) Five flipflop state register. TOfT? (Olj Bit time counter. TO is true during first bit time of a byte. A transfer to memory, i.e., a Store A, B, or X instruction. T!·1 TS (21) True for the byt~ time after SN in addition and subtraction. Controls writing of OV and CY. -14- GLOSSARY TX (18 ) Intermediate signal used in shifts, rotates, and bit manipulation instructions. UT (04 ) True during time location 200 is being read from memory. WD (23 ) write data. memory. Data to be written in the WT (23 ) write time. Time to write in the memory. WO/~.:j7 (17) Wo is least significant bit. utility register. w register. A general -15- (Output) BLOCK DIAGRM1 The major logical elements of the system are shown in the block diagram on page . The KENBAK-l computer differs internally in its structure from the majority of computers in these two ways: 1. The computer is serial. Data is read, or written, from the memory one bit at a time. Thus i t takes eight clock times to read a byte from the memory. 2. The programming registers {A, B, X and P} do not exist as actual hardware registers. Instead, a fewer number of hardware registers are time-shared to provide the necessary data manipulation. In the block diagram, the source of the clock signals is an RC multivibrator which runs at twice the fundamental system frequency. The clock pulse generator produces the basic system clock, CP, which is a square wave. One bit time lasts from one positive-to-ground transition to the next such transition: ,. .. + - \.,r I I GND- ---l I I 1'-_...1 I~ BIT TIME I I There are eight bit times: T6, and T7. TO, TI, T2, T3, T4, TS, These are generated by the bit time register in which a single bit shifts. Following T7, TO is generated -16- MULTIVIBRATOR CLOCK I---t PULSE Fl,F2 BIT TIME T.O REGISTER T7 MEMORY ADDRESS REGISTER DESIRED LO REGISTER NEXT STATE DETERMINATION eP,C7 GENERATOR STATE S HALT SWITCHES eM COMPARATOR CONTROL LC JUMP ADDRESS JC CONDITIONS A7 MR REGISTER WO--.~ ADDE R/ SUBTRACTOR TO T1 INPUT VI REGISTER OVERFLO\V +CARRY CONTROL ..-----~ SHIFT + BIT INST. A7 10 DELAY Q,5 LINE 0 OLO MEMORY Q,S MEMORY OUTPUT SELECT WRITE TIME DELAY LINE T9 Y7 OV,Cy DATA LIGHTS DATA SWITCHES Fl CLOCK F2 DRIVERS MR DLl WO K LC SYtoJCRONIZATION REGISTER CONTROL SWITCHES MR again and the cycle repeats indefinitely. L ______-----lr ONE BYTE TIME A byte time lasts eight bit times, from the start of TO to the next start of TO. It is useful to have a clock pulse which only occurs during T7 bit time. This is C7: The memory for the computer consists of two delay lines or shift registers, each of 1,024 bits. each will hold 128 bytes of information. Therefore Bytes with addresses 000 to 177 (octal) are in delay line 0 and bytes with addresses 200 to 377 (octal) are in delay line 1. Delay line 0 Delay line 1 -t>1 177 176 -t>1 377 376 175 I 375 1 ~I 1 ~I 174\ 002 001 000 f-t> 374 202 201 200 t-r> After byte 177 is read, byte 000 will appear in delay line o. At the same time that byte 000 is read from delay line 1, byte 200 is read from delay line 2. Circulation of the information within the delay lines in continuous. It never stops. Eight bits are required to address a byte since 2 8 = 256. The most significant address bit, A7, selects the delay line. The seven least significant address bits select a position or a time slot within the delay lines. The memory address register (the L register) shifts serially and counts one each byte time. The counting, or adding one, is a serial process. Whenever reading or writing is to occur, the desired address is set up as the serial signal R. When the seven least significant bits of R are equal to the seven least significant bits of the memory address register, then the -19- next byte time is when the data for the desired address will be at the input and output of the memory. The most significant bit of R is used to determine A7, the delay line selection signal. The memory address register is, in effect, one byte time ahead of the memory. The comparison between the memory address register and R is summarized by the signal eM during T7. exists if eM is true at this time. not exist if Comparison Address comparison does eM is false at this time. As an instruction is executed, the computer proceeds through a series of steps. to find address 003 For example, the computer has (the P register), then i t has to read and update the value of P, then it has to find the instruction, read the instruction, etc. While it is doing these things, the computer is in certain states. The fact that the computer is in a given state defines what it is to do while it is in that state. The data read from the memory and other conditions including the current state of the computer defines the next state. Thus the computer advances from state to state. The computer has 29 valid states and 3 invalid states. Should an invalid state occur, which it shouldn't except when power is turned on, a valid state is generated next. The 32 total states result from the combinations of five flipflops, 54, 83, 82, 81, SO. The five signals are applied to decoders which generate 32 outputs. -20- Only one of these outputs can be true at any given time. This is the current state of the computer. A state always starts and ends with the end of T7 (or the beginning of TO). It may last one byte time or it may last for many byte times. The names for the decoded state outputs are two letter symbols which start with S or Q. No signal other than a state signal is assigned a two letter code starting with S or Q. The nature of the decoder is such that the single true output is at ground while all of the rest of the decoded state signals are positive. Hence the outputs of the decoder are labelled Si and Qi to conform to positive logic. The next state of the computer and when it advances are determined by many factors: , ...... The current state, 2. Has the desired address been found, 3. Is a halt required, 4a The instruction and its addressing mode, 5. Are tIle jump conditions met, 6. The panel or control switches. There is a serial adder/subtractor with two inputs, A and B. In subtraction, B is subtracted from A. Overflow and carry out of a byte are detected, and in addition and subtraction instructions, used to update the OF and CA bits -21- in locations 201, 202, and 203. Most of the time, the I register is used as the instruction register to hold the first byte of the instruction. It is also used to hold the data for storing into the memory and for manual console operations. Except when infor- mation is being transferred in or out serially, the I register does not shift. The W register is a general purpose working register which holds data, addresses and operands. discussed at length later. It ~ill be Shift operations, for the Shift and Rotate instructions, are performed in it. Except for some bit times during these instructions, the W register is always shifting. The memory (two delay lines) have their outputs connected to their inputs so that data is retained or held. New information is entered in different ways, but the usual way is through the use of the Write Data and Write Time signals. New data, equal to Write Data, is entered into the delay line specified by the A7 address bit when Write Time is true. The input control for delay line 1 allows some special information to be entered into it alone. The states of the eight data switches are converted to a serial signal, BU. This is entered into address 377. The Clear pushbutton will erase the contents of address 377,to all zeroes. -22- The overflow and carry bits are entered into location 201, 202, 203 by direct entry through delay line 1 input control. The actual delay lines used are MOS shift registers which require two clock signals out of phase with each other. One occurs during the even bit times and the other occurs during the odd bit times. Several of the front panel control switches require some "cleaning up" before they can be used. After the contact bounce is eliminated they are used in the next state determination to control the reading and entry of data, the display of data, and starting and stopping of the computer. The data to be displayed in the lights may originate in the W register or in the memory. -23- STATE DIAGRAM The state diagram for the computer is presented on pages ~, ~, and 27. State names which start with S pertain to automatic operations of the computer or the Run mode. State names which pertain to manual opera- tions start with the letter Q. Of the three pages of state diagrams, the first page pertains to manual operations and automatic operations which are common to one and two byte instructions. The second page involves only two byte instructions and the third page is for one byte instructions. A state lasts for one or more byte times. It always starts with the beginning of a TO and it always ends with the end of T7. as a circle. A state is represented in these diagrams Directed lines, the state transitions, interconnect the states. Each line is labelled with logi- cal conditions under which the transition occurs. All of the lines which leave a state must have a logical sum which is equal to 1. Otherwise the computer might become trapped in a state with no valid exit. Also, if more than one line leaves a state, the logical product of any two must be O. Otherwise the logical transition would not be clearly defined. -24- COMMON AND MANUAL OPERATIONS ...-----. ~ su X5= EN+DA+DD TWO BYTE INSTRUCTIONS ONE BYTE FROM SO INSTRUCTIONS SA When the computer finishes any instruction, the SA state results. This may be regarded as the start of the next instruction. In state SA, the desired address is 3 which is the address of the P register a Therefore the function of state SA is to locate the P register. If, during T7, the comparison signal, eM, is false, state SA will be regenerated for another byte time. If the comparison signal is true, then the next state will be SB. SB State SB lasts one byte time. While it is true, the P register is being read from the memory. The value of the P register being read is the address of the instruction which was last completed. The P register increment control circuits, through signal PO, have a value which tells how many memory locations this, last instruction occupied. This increment is added to the old contents to obtain the address of the next instruction. The sum is written back into the memory and is also transferred to the W register. At the conclusion of state SB, location 3 in the memory and the W register both contain the address of the next instruction. If signal ED is true at the end of SB, this indicates the computer should stop, either because the last instruction was a Halt or because the Stop button was depressed. -28- Then the next state is QC. If the signal ED is false, the computer continues its automatic operations by going to state se. se The function of state SC is to find the next instruc- tion. The desired address is in the W register and this is compared to the memory address register until a compari- son is found. When eM is true at T7, the state register advances to state SD. SD During state SD, a one byte time state, the first byte of the instruction is transferred to the I register. The data path for this is through the A input of the adder. If 13 + I2 is true during T7, the instruction has two bytes. In this case the next state is SEe If I3 + 12 is not true, the instruction being read from the memory consists of only one byte and then the next state is SU. (The signal to use is 13 + 12, and not 12 + II, because the instruction still has one bit position to shift in the I register. This will occur at the same time that SD ends.) SE During SE, which lasts one byte time, the second byte of the instruction is transferred to the W register. is one exception to this rule. There If the instruction is Store Constant (also called Store Immediate), the W register is -29- loaded with the address of the second byte of the instruction and not with the contents of the second byte. This is accomplished through the adder inputs. A B SUM Store Immediate WO TO Address of second byte Not Store Immediate MR 0 Contents of second byte Since the W register contained the address of the first byte of the instruction, in the Store Immediate instructions the sum will be the address of the second byte. In all other cases the sum will be equal to the contents of the second byte. In either case it is the sum which is transferred to the W register. Depending upon the addressing mode and the type of instructions, state SE may be followed by four other states. For indirect addr~ssing, SF follows. For indexed addressing (without indirect addressing) SH is next. For direct memory addresses to find operands, state SK follows. If no operand is to be found, state S~1 follows. Generally, regardless of the addressing mode, all of the two byte instructions will involve state 8M which is a search for the A, B, or X register. If the instruction will change A, B, or X, then during 8M the W register will contain the operand. If A, B, or X is to be stored in memory, then the W register will contain the address of -30- the location where A, B, or X is to be stored. If the instruction is a Jump, then W will contain the target address during SM. The bit manipulation instructions are two bytes and have memory addressing, but they do not advance to state 8M because they test or modify a location in the memory and not the A, B, or X registers. SF State SF is a search for an indirect address which is in the W register. When found, state SG results. SG During SG, the contents of the indirect address location are transferred to the W register. is required also, state SH follows. If indexing For a Jump Indirect or a Store without indexing, then 811 is next. Othenvise state SK for finding the operand follows. SH In state SH a search for the X register, address 2, is made. When found, the state counter advances to SJ. State SH is preceeded by SE if there is indexing without indirect addressing. It is preceeded by SG if indirect addressing is also involved. SJ During SJ, a one byte time state, the contents of the X register are added to the contents of W. -31- The result is stored in W. For Store instructions, state SM follows. For other instructions, SK is the next stateo SK On entering state SK, the W register contains the address of the operand. This may have been directly from the instruction or i t may have been derived from indirect and indexing operations. Using this operand address, a search is made for the operand. When found, state SL follows. SL For the non-bit manipulation instructions, the W register is loaded with the operand. At the end of the byte time, for these instructions, state SM is next. For the Set 0 or Set 1 instructions, the designated bit is set during SL. For the Skip on a and Skip on 1 instructions, the P register increment control is set as necessary. The bit manipulations are then finished and state SA is the next state. 8M State SM is a search for the A, B, or X register as defined by the instruction. (For Jump Unconditional instructions, a search is made for the A register.) For instructions which modify the A, B, or X registers, the W register contains the operand. -32- State SN follows. For instructions which will store A, B, or X in the memory, the W register contains the address where the data is to be stored. State SP follows. For the Jump instructions, the W register contains the target address. The target address is the jump address or the Ifmark" address. State SZ follows. SN The instructions which change A, B, or X do so during SN. The W register contains the operand. X is read from the memory. A, B, or The required operation is performed and the results are stored into A, B, or X. One byte time is required and then these instructions are finished. State SA is next. In the Jump instructions (see SZ and ST), the address in W is transferred to the memory to become the new value of the P register. SP To store A, B, or X in the .memory, the I register is loaded with the contents of A, B, or X. Since this destroys the instruction code in I, all of the remaining parts of the instruction can only be dependent upon the state. Upon leaving SP for state SR, the I register contains a byte to be stored in the memory and the W register contains the address where it is to be stored. SQ (See after ST) -33- SR In state SR the address corresponding to the contents of the W register is sought. When found, state 58 is generated. 58 In state 55 the contents of the I register are transferred to the memory. This state is used in the Store instructions or in the Jump and Mark instructions. In all cases it concludes the instruction and state SA follows at the end of the byte time. sz (Out of sequence) In the Jump instructions, after the A, B, or X register is located in state 8M, state SZ follows. The jump conditions are evaluated during this byte time while A, B, or X is being read from the memory. jump is to be made, state SA follows SZ. If no If the jump is to be made, state ST follows. ST State ST is a search for the P register, address 3. In the Jump instructions \'1ithout urnarking U , state SN follows after address 3 is found. For the Jump and Mark instructions, state SQ follows. SQ (Out of sequence) Two things occur during SQ. The I register is loaded with the value of. the P register plus 2. the return address. This is At the same time the P register, -34- address 3, is set to the value of the target address in the W register. This target address is where the return The P register increment address will be deposited. control is set to add one so that the next instruction will be taken from the address following the target address. After state SQ, states SR, SS, and SA, all discussed previously, follow. SU (The five remaintng S states pertain to one byte instructions.) If the instruction read in state SD is a one byte instruction, then state SU follows. A search is made for address 0 or 1 When (A or B registers). found, the state register advances to SV. SV In state sv, the A or B register is transferred to the W register. For the Halt and No-op instructions this state is the last and state SA follows. sw Shifts and rotates are executed in state SW which lasts one byte time. Following SW is state SX. SX A search for address 0 or 1 (A or B) is made. When found, the next state is SY. Sy The shifted or rotated value of the original A or B register is written back into location 0 or 1. This finishes the Shift and Rotate instructions and the next state is SA. -35- SZ (See after 55) QA (Not used) QB (See after QF) QC When the computer is halted, state QC is the idle state. If one of the control switches (Store Memory, Display Address, or Read Memory) is pushed, the control advances to state QD. During IN time of QC, the I register is always loaded with the contents of location 377. If the Set Address switch is pushed, generating EA, the contents of the I register are transferred to the W register. If the Start button is pushed, control advances to state QB. QD In state QD the address which is equal to the contents of the W register is sought. When found, state QE is nexta QE In state QE, the action depends on which button was pushed: Store Memory (EN) Transfer I to I"1emory I Add 1 to ~'V Display Address (DA) Transfer W to K Read I/lemory (DD) Transfer I'lemory to K, Add 1 to Y'~ State QF follows after one byte time. -36- QF The state register control waits at QF until the control buttons are released. ~Vhen they are released, state QC is generated. QB (Our of order) State QB "rernembers Jl that Start was depressed but prevents control from advancing until Start is released. When Start is released, state SA is generated. -37- DEFINITION OF LOGIC ELEMENTS The logical circuits for the computer are implemented with 14 types of integrated circuits. has a distinctive schematic symbol. Each type In the following pages these symbols are defined. An integrated circuit package has 14 leads for the type 7442). (16 leads Pin 7 is ground and pin 14 is +5 volts (for type 7442, pin 8 is ground and pin 16 is +5 volts). A package may contain a number of independent circuits. Each circuit is defined by its input and output pins and a typical input-output relationship is given as a logical expression. Additional information on these circuits can be found in manufacturers' data sheets or handbooks. Some manufacturers of these circuits include Motorola Semiconductor National Semiconductors Texas Instruments Signetics Fairchild Semiconductor though this is not an exhaustive list. Each manufacturer has a distinctive nomenclature for his units though they all generally involve the four digit 74-- number. In the actual schematics, the input pins may be ordered differently from the definition. -38- QUAD 2-INPUT NAND GATE 1 7400 A~C ~ 6 B C=A+B QUAD 2-INPUT NAND GATE, OPEN COLLECTOR :=ttYC= A +B C 7403 ~ 6 12 =itY- WITH EXTERNAL LOAD TO +5 V HEX INVERTER 7404 A~B~~~~~ B=A QUAD 2-INPUT AND GATE 7408 :=±[y-C =i1Y- ~_lL 9 ~ C=A·B NAND GATE 7410 3 9 6 4 5 10 11 8 D=A+8+C HEX INVERTER A--1{>P-B B= A BUFFER 7416 ~+-4-- ~ ~ ~ ~ WITH EXTERNAL LOAD TO +5 V DUAL 4-INPUT NAND GATE A 1 B ft C 4 5 7420 La o 8 E E=A+B+C+D 8-INPUT NAND GATE 7430 A ........ B -...... C D E F G 11 H 12 8 J J=A+B+C+D+E+F+G+H BCD TO DECIMAL 7442 DECODER D+C+B+A O+C+B+A O+C+B+A D-I-C+8+A O+C+B+A O+C+B+A O+C+B+A O+C+B"+A D+C+B+A i5+C+B+A DUAL 2-WIDE 2-INPUT AND-OR-INVERT GATES A 2 B 3 7451 __E ~8 C---.. D 4-WIDE 2-INPUT AND-OR-INVERT GATE A 1 B 13 7454 c o XJ-M-8- J E----t F ,.,.~ ~~ J =A·B+C·O+ E·F +G·H QUAD 2-INPUT EXCLUSIVE OR GATES ~=brY-C ~ C=A·B+A-B 7486 ~3021 DUAL TYPE D 7474 7479 FLIPFLOP 4 SET DATA 2 10 5 Q 12 9 Q 11 8 6 CLOCK 3 1 RESET 13 Q IS EQUAL TO DATA JUST PRIOR TO LAST 0 TO 1 CLOCK TRANSITION SET AND RESET ARE NOT USED 7495 4 BIT SHIFT REGISTER OS 1 MODE 8 CLOCK 2 9 LOCK 1 6 2 ZO EQUIVALENT CIRCUIT WHEN h\ODE IS 1 - 00 13 01 Q2 03 12 111 101 - - -- ,..- -- - u ~ - ~ 0- -- 21 31 ZO Zl 51~ Z3 WHEN MODE IS 0 00 Q1 Q2 03 13 12 11 10 1 os 9 CLOCK 1 LOGIC SCHEMATICS In the following pages, the complete logic schematics for the computer are given. Each page is given a "local" two digit reference number which is used to cross reference the sheets. Some signals are so widely used that they are not cross referenced. These include CP, C7, TO, TI, T2, T3, T4, T5, T6, T7 (sheet 01) Original state signals, Si and Qi (sheet 09) Original 17, I6, IS, I4, I3, I2, II, IO (sheet 14) In addition, signals which originate and which are used on the same sheet are not cross-referenced. Cross referencing is only backwards, from use to source. Each logic element shown in the schematics contains a one, two, or three digit number which is the number of the integrated circuit package. This identity etched on the printed circuit board. -42- nurr~er is 2 T7 79 1 6 4 13 12 2 TE 3 TE 90 F2 5 6 1 9 11 10 8 Fl 10 12 8 25 CT T1 11 90 TT +S +5 9 8 13 +5 CP ~-')----"--- C 7 ).;1.... 1 TO T1 T2 13 T7 T4 T5 T6 T7 13 6 8 9 8 CP CP 9 CP CP +5 T4~1:;-;:;;-2....- Tell 01 L7 L6 LS L4 L3 L2 L 1 LO 13 8 1 6 9 11 2 2 1 6 3 4 5 12 11 10 4 5 111 2 3 -LO- -LO-Cp- -Jl7LO-4--\o-o1l 5 LC--1-4 10 8 LO 12 LC T7 CP 11 101 13 LC 9 8 4 3 2 -4 ~6 T7 5 1 CP 3 if __9~ LO C 10 8 3 ._. C ~ ~eM ~~ +5 23 "p - L 100 ------" CP ~ '-- T7- 12 13jj::l~ 02 9 ~11 QC~. 8 3 'tAR A7 24DlO MR 03 +5 +5 INPUT. -L- o TO--~ l---l---=--~.-.-----, T1 T2 8 T3------· 11 6..----BU T4 TS 3 T6 -.L- 7 T7 05 4 4 8 4 4 4 8 4 X4 4 4 06 OUTPUT '*7 +5 13 5 3 1 9 K7 K6 KS K4 13 12 11 10 6 KS 6 8 1 9 6 K7 K6 K5 K4 CP KS K3 K2 Kl KO 13 12 11 10 11 8 9 K3 K2 Kl KO CP 6 6 Xl~ 3_ 17 WO 6 3 X2 MR 6 X3 24 DLl 6 24 -4~ ~L1 13_. 07 4 4 4 4 DA EN------a DA-..... EN+OA+DD DO..----......... EN+OD 4 DO 4 EN 4 EA 12 41N~ ~......8----IN+CL 4IN~- BU~--IN+BU 4GO l~6_GO ~~-QC,IN 08 15 14 4 SO 5 10 JSO 2 3 C7 132 SO 6 51 9 QC 3 8 13 12 1 10 10 JSl 12 C7 11 125 8 132 51 13 15 14 4 13 10 JS2 2 52 5 C7 3 S2 6 10 JS3 12. S3 9 C7 11 53 8 131 3 SA 08 SX 8 12 Sy 58 51 SV 1 10 131 126 9 10 1 13 3 13 4 10 JS4 2 C7 3 8 12 54 5 6 130 S4 1 2 3 4 5 6 7 9 SM SH SK SF SN SJ SL SG ~ C7 ~ 5 108 +5 I 0 C7 15 14 13 12 1 3 8 2 3 4 5 6 SP 5W SC SD 5Z _7- 50 9 128 JS4 JS3 JS2 11 G2 J SI 5 1 2 SF _ 4 ~ G4 6~8 G5~3~JSO JSOA-. 12 JSOB 11 10 sc SF SK 6 Gl 13 S8 22 ED SO 6 8 G2 SU 3 8 --G3 n- sv---ue~8--1 -+ --~------sv 66 _6__ Rd __ G4 10 11 sz 3 ~'--G5 21JC 13 Sf o--6_- JS4A eM 23 12+11+10 ~8~_-._.........- JS4B 3 1"J!",,.,...,,,,~--. . JS3B SL L-_ _-.-.-_.--:............... - - - - - - - - - - - SU+SX 13 QC 8GO C1" 8 lna..- 16 i4 12 JS3A 1 ST~ eM 13 4 5'1, 3-tj§~6 - - " " - - w 11 13 SM· 11 14 is 15 112 6 eM 10 9 56 8 JS2A 8 JS1A 8 eM 11 8 EN+OA+OD 3 11 JS4A 14 13 SE 16 110 SO 13 QC 8GO 3 11 5 4 8 JSOB SG 14 15 11 12 3 CM- SG 4 6 eM 3 SG 5 6 x-.-----SM 12 ...-.-- ST 10____ SB x Jo-__ 11 QC 13 17 13 12 11 16 15 14 13 19 SUM 1 FT _ 6 13 8 6 2 17 11 101 8 9 CP 9 -CP 6 12 10 20 2 16 15 13 14 12 11 10 QE 8 8 aC+IN ~. 1 7 - - ° - . - - - - - - - - - - 17 ~2---17,16 17 16 ~')-..8-_~!t-------- 17 + 16 12 12 ~---=-- 17,16 -d@-1-1-------------i2 10 ~_1_2----------d 10 13 ~_-8-------~...........- 13 15 --·~i~:>(} 6 --...........-.---....----..........- - - - IS 14 i7+i6~ 14 14 15~ 14 13 11· 12 11 10 4 1 6 (17+16)15,14,13,12,11,10 8 11 10 :x'). :l;. ;:;;.O 16 ~...!8L- i6 17 ~..!.12~ --, 17 'ft,...,":;6~ 14 _ 12 3-tlO ~4~_ _ 17,16 17+16 ~3~ _ _-aiii5-tl0 ~_6--. _ _ 17,16 14 ~--112 14 ~.:l..'" 11 ~ . 13~ 11 14 17,16 10 112 1.- _ ~8SL- 17+16+14,13 . 3 - 13+12 12 i5~11 14 15 1 14~3 14 9 11~8 15 112 14 is 21 12 11 6 J J - - - -..... IT 14 15 6 12 10 12+ IT+ IO - - - t r - - - - - - ' 23 16 15 9 12 10 13 L.JII--8- - 110 .o--l_2_1IiIIIlA 13 1415 10 lUI 11~6~' - 10 5 12 ~ ~ 12 11 13u--.......... 16 W7 W6 WS W4 W3 W2 Wl WO JW7 1 8 HF 6 9 73 JW3 CP CP HF 1 8 6 9 72 CP CP 2 2 W7 W6 W5 W4 18 RR 3 12 ...-.. 4 5 61 6 HF sw SW 8 S8 SE SG SJ sr 19 SUM Q 10 6 13 WO 1 2 12 10 11 9 71 8 JW7 QE SV sw 15 17 16 17 15 i6 18 LS JW3 17 TX 13 TX T7 1 6 2 2· 15~i5 14~T4 13~i3 8 9 3 4 CP CP 5 3 6 11 8 ------------------RR 12 TO C16-r 13 1 17 12_-8T 1.1- 2 14 C171; 18 20 A 2 1 B 3 6 SUM 23SN~ 13 ~Lr--6- s - - ADD 20 A-""-J CR OF c T7 CR 5 11 ~4. ")0 6 .~_~---,I U 0 '.' 9 8 +s 19 SN-··~-· 14--- 11 A 15 SE 8 B 15 SE SE SN SN QE QE sa 5 86 6 -~ sa S8 S8 20 17 16 C7 +5 19 OF C7 3 MR JC 21 PF PT PO 13 SB_4~.-.Il 13 ST----5~ 1 8 CP 6 9 CP 345 D PF lOJB8 9 43 KP 2 1 3 5 PT KP 11 4 11 12 su sa 3 MR 15 i6 11 sV__ 1 --.Ji 3 6 KP _ 15 17 2 14 fa 13 ED 11 10 ----.--""-'"-t44 9 8 QC~ 9 55 . nr ~'- _ 10 12 s 8 HT 3 ED 5 ED 6 +5 22 & - - - - - - - - - - - - - SN 17 14 1 ,16 13 V/K 14 3MR -~13 ~ '; 31 .' 11 WL _ 8 QE+EN 12 19 SUM WJ 17 WO WK---- .-~----10 WL ---------. 9 ~8......-----"'D --- 16 BP.A WJ WK ~---WT WL 14 i7 8M r----------=-------~ 12 + IT + I 0 14 i2 -1Lt -;;-t-=-'y } ro-Lr-../ 11 14 _ 1 f::'\~ 12 23 V/T 3 3 . .~~-JDLO A7 8 23 WT 3 A7 6 21 1S 8 21 TO OV 21 T1 CV JDL 1 DLl CL+IN 11 +5 21: R2Dt _ .6 ....:-...; 51 ... V JDlO ~ ~ 4 I .---------5 1,024 BITS L2.? 31 01 7n 02 +5 <it LR~ 13 51 lLolo 51 -5 -s +5 21: R2 JDLl . J 2 50 3 01 1,024 BITS 02 +5 9 1"-'"5~---...,;lO__~ DII -5 -5 +5 I R25 CR7 --------CT +s I 1 I F2Fl 5 R9 Rl1 R7 R14 3 R10 R12 02 ~01 CR3 CR4 CR2 CRS CRl ~_ _C_R-...6,-{)I.-,_...-_..... R8 R13 -12 25 I I I I I _____ ..J ,r I ~ QlOO ~~I~~ OHHr::> ~1~li(~ ~ ~ . ) -.J i TlOO ~ ~ II? .. • "'"'J J. • • • . ; , ~~O c~ ell.i... '\0c~nl}o i +OV II ) u 1 21tl(g CRIOrO/ T8too ?,3.,t ./','o Tl . -2. <....A.) ~10 . C:--RI02. / + k• ~'·f(103 C~!0<.1 • • • • .. ( T2.. ,! I I CRt04 ,n~·' C4 t}o T1t eJ!! h 1 J . J I I I , ) I I i c~q,iP I- , . ---..... 07"610\-' (CIlASSiS) R EAT<. Pl~~E"1 L\J&1T ~ • • • • POWER SVPPLY ASSV L ~) ".. ~')~dlik:'& IL L " Ci~h05 . . . . .,J.li .I.. ~\ ..."'" -.r"tl~i!:'<"""" Cjll!'i~ ., .---- TiOi I I I o ~':;, ~l f;o cit ~b c:':i fio I (,..1 ~ I. I r-----:....:..J I I I ---I ~ L.06tlC. !>l> ASSY (9 " ... :) -t2. V JJ -5\1