Manual / Guide · 1971
KENBAK-1 Programming Reference Manual (1971)
The KENBAK-1 instruction set, addressing modes, registers and front-panel operation.
Manual / Guide · 1971
The KENBAK-1 instruction set, addressing modes, registers and front-panel operation.
Programming Reference Manual KENBAK-l Computer KENBAK ~ o. BOX 49324 LOS ANGELES, CA. 90049 COPYRIGHT KENBAK 1971 Preface This manual is a summary of the KENBAK-l computer programming characteristics. The reader is assumed to be acquainted with the general theory of digital computers. Other manuals published by KENBAK have as their subjects the general theory of computers, programming of the KENBAK-1, and the maintenance and theory of operation of the KENBAK-l e To correct errors or to clarify the presentation I revised pages will be issued from time to time. The list of current pages should be retained as it indicates the status of the manual. Pages are punched for a three ring binder so that the user may keep all of his material in one place with easy accessibility. Questions and comments are welcomed since that provides the feedback which tells how well the job is being done. Price: $2.00 PR-i 4/1/71 Programming Reference Manual KENBAK-1 Computer List of Current Pages 1 Revision 0 Page Dated Page Dated Page Dated PR-1 PR-2 PR-3 PR-4 PR-5 PR-6 PR-7 PR-8 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 PR-9 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 PR-17 PR-18 PR-19 PR-20 PR-21 PR-22 PR-23 PR-24 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 4-1-71 PR-10 PR-11 PR-12 PR-13 PR-14 PR-15 PR-16 Errata For which no revised page was issued NONE PR-ii 4/1/71 Programming Reference Manual KENBAK -1 Computer Table of Contents Page Introduction PR- 1 Memory Structure and Addre s si ng PR- 1 Special Memory Locations LNEG PR- 1 PR- 3 PR- 4 PR- 5 PR- 5 PR- 6 PR- 7 PR- 8 JUMPS (BRANCHES) PR- 9 SKIPS PR-IO SE-r BITS PR-11 SHIFTS and ROTATES PR-12 NOOP and HALT PR-13 Number Representations Addressing Modes Instructions ADD and SUB LOAD and STORE AND and OR Symbolic Representation of Instructions PR-14 Register-to-Register Operations Console Data Lamps PR-15 PR-16 PR-16 PR-17 PR-18 PR-18 PR-18 Console Data Pushbuttons and Clear PR-20 Address Control Lamp I Address Display and Set Pushbuttons PR-20 Table Look Up Relative Operand Addressing Input and Output Console Operations Power On-Off Switch Memory Control Lamp Memory Read and Store Pushbuttons I Start and Stop Pushbuttons Lamp Tests Example of Console Use Summary of Instruction Coding PR-iii 4/1/71 PR-21 PR-21 PR-22 PR-23 PR-24 INTRODUCTION The KENBAK-l is a serial stored program general purpose digital computer with a memory of 256 eight bit bytes. Internally the machine is binary two· s complement. Halt No-op, and Shift instructions require I one byte. All other instructions require two bytes which may start on either an odd or even address. MEMORY STRUCTURE AND ADDRESSING Each of the 256 bytes of memory is addressable. of their addresses is 000 to 377 (decimal 000 to 255). The octal range 8 Since 2 is equal to 256, one byte of memory can hold a complete address. The eight bits of a byte are always identified as: b7 b6 b5 b4 b3 b2 bl bO x x x x x x x x Binary to Octal Conversion Octal group 100 Octal group 10 Octal group 1 where the most significant bit is b7 and the least significant bit is bO. Octal group 100 never assumes a value larger than 3. SPECIAL ME·MORY LOCATIONS Nine memory locations are used for special purposes. They may be addressed and used as an operand location though the programmer must be aware that he may be interfering with the assigned special function. The special locations are: Octal Location 000 001 002 003 200 201 202 203 377 Purpose A Register B Register X Register P Register Output Register Overflow and Carry for the A Register Overflow and Carry for the B Register Overflow and Carry for the X Register Input Register PR-l 4/1/71 The A Register is the primary register of the arithmetic unit. Operations that can be performed with it include Load Store I Subtract I And I Or I Load Complement I Shifts and Rotates. is the secondary register of the arithmetic unit. performed with it include Load I Store I Add I I Add I The B Register Operations that can be Subtract I Shifts I and Rotates. The contents of the X Register are used in the Indexed address mode. Operations that can be performed with it include Load, Store I Add I Subtract. When not being used in Indexed addressing I the X Register can be used as an arithmetic register. The A, B and X Registers can all be used (singly I control the branch conditions. I not jointly) to The testable conditions include Non -zero, Zero, Less than Zero, Positive (including zero), and Positive Non-zero. The P Register is the Program Counter which shows the addres s of the next instruction to be executed. The Output Register I location 200, controls the Console Data Lamps when the computer is in the Run state. Locations 201, 202, and 203 contain the Overflow (OF) and Carry (CA) bits for the A, B, andXRegisters, respectively. b7 b6 b5 b4 b3 b2 bl bO o 0 0 0 0 0 CA OF Each time that an Add or Subtract instruction is performed, the Overflow and Carry bits for the register are updated. They remain in this state until the next Add or Subtract operation to that register occurs. The remaining six bits in each word are always set to zero when the Overflow and Carry are updated. The Load Complement and the Shift instructions do not alter these words, nor do any other instructions. Location 377 is the input location. Data from the Console Data Pushbuttons is placed here in both the Run and Halt states of the computer. PR-2 4/1/71 NUMBER REPRESENTATIONS Several choices exist for number representation including positi ve integer I signed integer I and signed fractional II The range of numbers that can be expressed in one byte in each mode is shown in the following table: Decimal Valld.L Octal Code Binary Code +255 377 a 000 11 III 111$ 00 000 000. Largest positive number +127 177 Smallest negative number -128 200 01 III Ill. 10 000 000. +127/128 -128/128 177 200 0.1 III III 1.0 000 000 Number Representation Positi ve Integer Largest positive number Smallest number Signed Integer Signed Fractional Largest positive number Smallest negative number The Jump (Branch) conditions of Positive, Negative, and Positive Non-zero assume one of the signed modes of number representation. The Jump conditions of Zero and Non-zero apply for all of the representations since 00 000 000 is the binary code for zero in all of them. As detected by the computer I Overflow is based on the signed representations. Since the binary arithmetic is identical in all of these representations I the Carry bit is not affected by the programming choice for number re"presentation. For positive integer representation the Carry is also the Overflow condition. The range of quantities can be extended by using more than one byte. PR-3 4/1/71 ADDRESSING MODES The Add I Subtract I Load I Store I Load Complement I And I and Or instructions have five addressing modes: 1. 2. 3. 4 5. 0 Consta nt or Immediate Memory Indirect I or Deferred Indexed Indirect Indexed I In the Constant I or Immediate I mode of addressing, the operand is the contents of the second word of the instruction. In the Memory mode of addres sing I the second word of the instruction is the a ddre s s of the opera nd . In the Indirect addressing mode I the second word of the instruction is the address of the address of the operand. In the Indexed mode of addressing I the contents of the second word of the instruction are added to the contents of the X Register to form the address of the operand. In the Indirect Indexed mode of addressing, the contents of the second word of the instruction are used as an address pointer to the contents of another I second I location. The contents of this second location are added to the contents of the X Register to form the address of the opera nd • In the Store instruction the operand address is where the data is stored. In Store Immediate instructions the data is stored in the second half of the instruction. The Bit Manipulation instructions have only the Memory addressing mode. The Jump or Branch instructions have Memory (called Direct) addressing or Indirect addressing. PR-4 4/1/71 INSTR UCTIONS In the following pages I the individual instructions are discussed. It is assumed in each case that the instruction is in location p and (if it is a two byte instruction) in p + 1. ADDITION (ADD) First Byte Second Byte Register 7 6 5 4 3 2 1 0 Addressing Mode A B 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 1 0 1 1 0 1 1 1 Immediate Memory Indirect Indexed Indirect I Indexed X 7 6 5 4 3 2 1 0 Address or Operand The operand is specified or located according to the rules for the addressing mode. The operand and the contents of the designated register are added together and the sum is placed in the designated register. The operand is unchanged in the memory (unless the oper.and was in the designated register itself). location 201 (for A) I The Carry and Overflow bits are updated in in 202 (for B) I or in 203 (for X). The P Register is advanced by 2 and the next instruction is taken from p + 2 • SUBTRACTION (SUB) Second Byte First Byte Register 7 6 5 4 3 2 1 0 Addressing Mode A B X 0 0 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 1 Immediate Memory Indirect Indexed Indirect I Indexed 7 6 5 432 1 0 Address or Operand The operand is specified or located according to the rules for the addressing mode. The operand is subtracted from the contents of the designated register and the difference is placed in the designated register. The operand is unchanged in the memory (unless the operand was in the designated register itself). The Carry (or Borrow) and the Overflow bits are updated in location 201 (for A) I in 202 (for B) I or in 203 (for X). The P Register is advanced by 2 and the next instruction is taken from p + 2 . PR-5 4/1/71 LOAD (LOAD) Second Byte First B yte Register 7 6 5 4 3 2 1 0 Addressing Mode A B 0 0 0 1 0 0 1 1 1 0 0 0 1 1 0 1 0 1 1 1 0 1 1 1 Immediate Memory Indirect Indexed Indirect Indexed X 765 432 1 0 Address or Operand I The operand is specified or located according to the rules for the addressing mode. The operand is placed in the designated register replacing the previous contents. The operand is unchanged in the memory. The P Register is advanced by 2 and the next instruction is taken from p + 2 . STORE (STORE) Second Byte First Byte Register 7 6 5 4 3 2 1 0 Addressing Mode A B 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0 1 1 0 1 1 1 Immediate Memory Indirect Indexed Indirect Indexed X 7 6 543 2 1 0 Address or Operand I The location to receive the data is determined by the addressing rules. The contents of the designated register are placed in this location replacing the previous contents. The contents of the register are unchanged. The P Register is advanced by 2 and the next instruction is taken from p + 2. PR-6 4/1/71 LOGICAL PRODUCT (AND) First Byte Second Byte 7 6 5 4 3 2 1 a Addressing Mode 1 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Immediate Memory Indirect Indexed Indirect I Indexed 7 6 5 43 2 1 a Address or Operand The operand is specified or located according to the rules for the addressing mode. Each bit of the operand is Anded with the corresponding bit of the A Register I according to the truth table below I and the result is placed in the A Register replacing the previous contents. The operand is unchanged in the memory. The P Register is advanced by 2 and the next instruction is taken from p + 2. Result lll:!Q. (Inclusi vel OR o o o 1 0 1 1 1 Second Byte Addressing Mode Immediate Memory Indirect Indexed Indirect I Indexed 76543 2 1 0 Address or Operand The operand is specified or located according to the rules for the addressing mode. Each bit of the operand is Or-ed with the corresponding bit of the A Register I according to the truth table above (see AND) I and the result is placed in the A Register replacing the previous contents. The operand is unchanged in the memory. The P Register is advanced by 2 and the next instruction is taken from p + 2. PR-7 4/1/71 LOAD COMPLEMENT (LNEG) Second Byte First Byte 76543 2 1 a 7 6 5 4 3 2 1 0 Addressing Mode 1 1 0 1 1 a 1 1 1 a a 1 a 1 1 1 a 1 1 1 Immediate Memory Indirect Indexed Indirect I Indexed Address or Operand The operand is specified or located according to the rules for the addressing mode. The A Register is loaded with the arithmetic complement (the value obtained by subtracting from zero) of the operand. This replaces the previous contents of the A Register. The operand is unchanged in the memory unless it had been specified as the contents of the A Register itself. Overflow occurs if the operand was equal to -128 (10 00 000). In this case the result obtained is -128. This overflow is not detected nor is the A Register Overflow bit in location 201 altered by the LNEG instruction. The P Register is advanced by 2 and the next instruction is taken from p + 2. PR-8 4/1/71 (JPD) JUMP DIRECT (JPI) JUMP INDIRECT (JMD) JUMP AND MARK DIRECT JUMP AND MARK INDIRECT (JMI) First Byte Second Byte 7 6 5 4 3 2 1 0 A Register B Register X Register Unconditional a 1 1 0 0 1 0 1 1 0 1 1 Jump Jump and Mark 1 0 0 1 0 1 1 1 0 1 1 1 a 0 1 1 Condition 7 6 543 2 1 0 Non-zero Zero Negative Positive Positi ve Non-zero Target Address or Indirect Reference to Target Address Direct Address (M emory) Indirect Addres s The IItarget" address is defined to be: Jump Direct or Jump and Mark Direct The contents of the second byte of the instruction Jump Indirect or Jump and Mark Indirect The addres s contained in the byte whose address is in the second byte of the instruction The Direct address mode is the same as the Memory address mode. The Indirect address mode for the Jump instructions is the same as the Indirect mode for the arithmetic and logic instructions. The designated register (A, B, or X) is examined to determine if the Jump Conditions are met (true). A Non-zero condition in the register means at least one bit is a One. A Zero condition in the register means that all bits in the register are Zero. The Negative condition means that b7 (the most significant bit) is a One. The Positive condition means that b7 is a Zero. The Positive Non-zero condition means b7 is a Zero and at least one of the remaining seven bits is a One. The Jump Conditions can be forced to be true by the Unconditional specification. If the Jump Conditions are true because the specified condition is true or because an Unconditional Jump is specified, then the next instruction is not taken from location p + 2, but from the target addres s in the Jump instructions or from the target address plus one in the Jump and Mark instructions. If the Jump Conditions are not true I the next instruction is taken from p + 2 • PR-9 4/1/71 In the Jump and Mark instructions I the value p + 2 is stored in the target address prior to executing the instruction in the location following the target address. Notice that the instruction will not be a Jump instruction of any type unless bits 2, I, and 0 of the first byte are either 011 , 100 , 101, 110 , or III even if the Jump Conditions are Unconditional. SKIP ON ZERO (SKP 0) SKIP ON ONE (SKP 1) Second Byte First Byte 2 1 0 7 0 1 1 Skip on 0 Ski on 1 Bit Position a 7 6 543 2 1 0 bO bI b2 b3 0 0 0 1 0 0 0 1 0 1 1 0 1 0 Memory Address b4 b5 b6 b7 1 1 1 1 First the location in memory whose address is given in the second byte of the instruction is determined. Within these eight bits I the one is selected whose position corresponds to the three bit code in positions 5 I 4 I and 3 of the first byte of the instruction. If the instruction is Skip on Zero and the selected bit is a Zero or if the instruction is Skip on One and the selected bit is a One, then the next instruction is taken from p + 4 and the next two locations in the not used. II normal ll instruction sequence are Either a two byte instruction or two one byte instructions may be skipped. If the Skip Conditions are not met I then the next instruction is taken from p + 2 • PR-IO 4/1/71 SET 0 (SET 0) SET 1 (SET 1) First Byte Second Byte 7 2 1 0 o 0 1 0 Bit Position bO bI b2 Set to 0 Set to 1 7 6 543 2 1 0 Memory Addres s b3 b4 b5 b6 b7 The SET 0 instruction forces a single bit in the memory to a Zero. The SET 1 instruction forces a single bit in the memory to a One. The address of the memory location is contained in the second byte of the instruction. The bit within this word is determined by the bit code in positions 5 4, and 3 of the first byte of the instruction I in the memory is changed except the designated one. It No other bit The P Register is advanced by 2 and the next instruction is taken from location p + 2. PR-ll 4/1/71 SHIFT LEFT SHIFT RIGHT ROTATE LEFT ROTATE RIGHT (SFTL) (SFTR) (ROTL) (ROTR) First Byte One byte instruction 76543 2 1 0 Right Left Shift Rotate A Register B Reqister 0 1 0 1 1 0 1 1 0 1 10 o 1 0 0 0 1 Place 2 Places 3 Places 4 Places 1 Shifts and Rotates may be for I, 2 I 3, or 4 places. Ann place Shift or Rotate is equal to performing a 1 place Shift or Rotate n times. The 1 place Shifts and Rotates are defined below. b7 b6 b5 b4 b3 b2 bI bO SHIFT LEFT 1 Original After c7 c6 c5 c4 c3 c2 cl cO c6 c5 c4 c3 c2 cl cO 0 ROTATE LEFT 1 Origirlal After c7 c6 c5 c4 c3 c2 cl cO c6 c5 c4 c3 c2 cl cO c7 SHIFT RIGHT 1 Original After c7 c6 c5 c4 c3 c2 cl cO c7 c7 c6 c5 c4 c3 c2 cl ROTATE RIGHT 1 Original After c7 c6 c5 c4 c3 c2 cl cO cO c7 c6 c5 c4 c3 c2 cl This Shift or Rotate is made to the A or B Register as specified. The P Register advances by one and the next instruction is taken from p + 1. PR-12 4/1/71 NO OPERATION (NOOP) One byte instruction First Byte 7 6 5 432 1 a 1 x x x x 0 0 0 The P Register is advanced by one and the next instruction is taken from location p + 1. HALT (HALT) One byte instruction First Byte 765 432 1 0 OxxxxOOO At the end of this instruction, the computer goes from the Run state to the Halt state. The P Register is advanced and ready to take the next instruction from location p + 1. PR-13 4/1/71 SYMBOLIC REPRESENTATION OF INSTRUCTIONS An instruction, including the operand address or specification, is represented symbolically in three parts. The first field is the basic operation such as ADD or SFTR. Preferred abbreviations for these operations were given with the instruction descriptions. The second field is the details of the basic operation, for example, nAif meaning to add to the A Register or B3 meaning to shift the B Register 3 places. The third field is the operand address except in the case of the Constant addressing mode which has a special representation illustrated below. Indirect addressing is indicated by the use of parentheses around the address CD The Index addressing mode is indicated by rr ,Xu. The third field for the fi ve addressing modes becomes: Constant Memory Indirect Indexed Indirect/Indexed C = Value of Operand DATE (DATE) DATE, X (DATE), X where DATE is the name of some location in memory. One byte instructions have no third field and may (Shifts and Rotates) or may not (Halt and Noop) have a second field. PR-14 4/1/71 REGISTER-TO-REGISTER OPERATIONS All of these operations are produced by a single instruction using the Memory addressing mode. They are special cases of the previously discussed instructions which result from the addressability of the A, B, X, and P Registers. Operation Symbolic Representation CLEAR A CLEAR B CLEAR X SUB A SUB B SUB X A TRANSFER A TO B TRANSFER A TO X TRANSFER B TO A TRANSFER B TO X TRANSFER X TO A TRANSFER X TO B LOAD B LOAD X LOAD A LOAD X LOAD A LOAD B A A B B X LEFT SHIFT A 1 LEFT SHIFT B 1 LEFT SHIFT X 1 ADD A ADD B ADD X A B B X or or or or or X or STORE A STORE A STORE B STORE B STORE X STORE X B X A X A B X This left shift operation is the same as produced by the instruction of the same name It When produced by adding the register to itself I Overflow and Carry are detected which they are not by the Left Shift instruction. Carry bit is set if b7 was a One and is reset if b7 was a Zero. The The Overflow bit is set if the original number was larger than 63 or smaller than -64 QI Otherwise the Overflow bit is reset. LOAD A NEG A LOAD A NEG B LOAD A NEG X LNEG A LNEG A LNEG A A B X The A Register is loaded with the complement (the value obtained by subtracting from 00 000 000) of the specified register. Overflow I undetected, occurs when the original number is -128 when the result produced is also -128. PR-15 4/1/71 A + B TO A ADD A SUB A ADD A SUB A A - B TOA A + X TO A A - X TO A B + A TO B B - A TO B B + X TO B B - X TO B ADD B B B X X A X + B TO X X - B TO X SUB B ADD B SUBB ADD X SUB X ADD X SUB X A AND B TO A A AND X TO A AND A AND A B X A OR B TO A A OR X TO A ORA ORA X JUMP TO A + 2 JUMP TO B + 2 JUMP TO X + 2 STORE A STORE B STORE X P P P X + A TO X X - A TO X A X X A A B B B Storing a number n in the P Register under program control causes an unconditional branch or jump to location n + 2 • TABLE LOOK UP Using the contents of the A, B, or X Register as an Indirect address produces a result which has been called Iltable look up LOAD A If • The operation (A) replaces the address in the A Register by the contents of that address G Similar operations can be produced by the B and X Registers or by combinations of the A, B I and X Registers. RELATIVE OPERAND ADDRESSING Using the Indirect Indexed addressing mode with the P Register as the Indirect address location creates a condition which could be called IIrelati ve operand addressing 'f • The operand address will be a If distance II from the instruction itself which is given by the contents of the X Register. PR-16 4/1/71 INPUT AND OUTPUT Input from the Console Data Pushbuttons to the program and output from the program to the Console Data Lamps can occur while the computer is in the Run state. All input appears in location 377 whose contents may 8 be tested with the Skip instructions or whose contents may be transferred to the A, B I or X Registers. It must be remembered that data will appear in location 377 while the operator is in the process of forming his input e 8 If the input data is not to be used until the formation or entry is completed, one of the bits should be used as an interlock signal. The contents of location 200 are continuously displayed in the 8 Console Data Lamps when the computer is in the Run state. A transfer of data to 2008 is equi valent to the output of that data to the Console Data Lamps. If the computer goe s from the Run to the Halt state I the contents of location 2008 are displayed until the operator makes another choice. PR-17 4/1/71 CONSOLE OPERATIONS The Console switches and lamps provide the means to control the computer I to load programs and data I and to receive output (frontispiece) . Power On-Off Switch The Power Switch controls the line voltage to the computer. Data in the memory is lost when power is turned off. When power is turned on, ra ndom data will appear in the memory u Since the computer uses very little power (40 watts), it can be left on without damage or significant expense. No indicator light per se is used to indicate the power status. If any of the data and control lamps are on, then power must be on. If power is thought to be on and none of the data or control lamps are on, pushing the Clear Pushbutton will cause the Input Lamp to turn on if power is available. Also the Start I Read, Display I or the eight Data Pushbuttons can be used to test the power condition. The fan can also be heard when power is on. When power is turned on, the Start Pushbutton should be depressed. If the computer stays in the Run state be depressed. I then the Stop Pushbutton should also These operations will initialize the internal control circuits e Console Data Lamps The eight Console Data Lamps receive their information from one of four sources as indicated by the Console Control Lamps I page PR-19 & If the Input Lamp is On, the Console Data Lamps are displaying the contents of location 377 which is the location in memory where input is assembled 8 If the Address Lamp is On, the Console Data Lamps show the contents of e the Address Register which is used for reading or storing data in the memory. If the Memory Lamp is On, the Console Data Lamps show the contents of a memory location which has been read. If the Run Lamp is On, or if none of the Control Lamps are On, the Console Data Lamps show the contents of location 2008 which is assigned as the program output register. PR-18 4/1/71 DATA P. B. TO PROGRAM LOCATION 377 .... - - - - - - - "-- ADDRESS REG ~- i r-- J , MEMORY I I I 1 IL __ . J ' INPUT DATA LAMPS RUN FROM PROGRAM CONSOLE DATA FLOW LOCATION 200 PR-19 4/1/71 Console Data Lamps Show When Control Lamp is On Contents of 377 Input Contents of 200 8 Run or None of the Control Lamps 8 Contents of Address Register Address Contents of Memory Location Memory Console Data Pushbuttons and Clear The Clear Pushbutton erases the contents of location 377 00 000 000. A Data Pushbutton sets the bit position in 377 corresponds to its respective number. 8 8 to which If a One is -entered by mistake I Clear must be used to erase location 377 Ones must be re-entered information I to 00 000 000 and the correct 8 Between the entry of different bytes of 41 Clear is used to erase the previous data. Entry can occur during the Run state. Normally I the Console Data during the Run state 8 During the actual interval while the Clear or Console Data Pushbuttons Lamps are displaying the contents of location 200 e are depressed, the Console Data Lamps will predominantly display the contents of location 377 8 0 In the background, as a fainter light, the contents of location 200 will also be displayed. In the Run state I entry S of data to location 377 must be accompanied by a stored program which 8 will interpret and make use of the data. In the Halt state, the data entered into 377 can be used to set the 8 Address Register or it can be stored in the memory at locations determined by the Address Register. Address Control Lamp, Address Display and Set Pushbuttons While the computer is halted, data may be entered or read from the memory where the address to be used is held in the Address Register. Data is entered into the Address Register by the Address Set Pushbutton. The source of this data is location 377 8 which in turn is determined by the Clear and Console Data Pushbuttons. The contents of the Address Register may be caused to be displayed by the Address Display Pushbutton. This will be the next address. When reading or storing data in the memory I the contents of the Address Register are incremented by one for each depression of the Memory Read or Memory Store Pushbuttons. PR-20 4/1/71 When the computer goes into the Run state the value in the Address Register \lvill be changed in an unspecified way. Memory Control Lamp, Memory Read and Store Pushbuttons While the computer is in the Halt state, data may be examined (read) or be entered (stored) in the memory. This may be done one byte at a time. The memory location to be used is contained in the Address Register. For storing data, the source of the data is location 377 • In reading data I 8 the Console Data Lamps will display the information. Each depression of the Read or Store Pushbutton will cause the Addres,s Register to advance by one. Start and Stop Pushbuttons After a program and data have been loaded into the memory, the computer can be made to go into the Run state by the Start Pushbutton. In the Run state I the computer is executing a stored program. The Run state will last until a Halt instruction is encountered or until the Stop Pushbutton is depressed. The computer can be made to execute instructions one at a time, stopping after each instruction is finished. To do this, hold the Stop Pushbutton depressed and push and release Start. The Stop Pushbutton can then be released. The computer will have executed one and only one instruction. If the P Register is examined while the computer is halted, it will show the address of the next instruction to be executed. Similarly I if the P Register is being loaded, it should be set with the address of the next instruction to be executed. PR-21 4/1/71 Lamp Tests To test whether a lamp is burned out push the Pushbutton in the table below. The lamp should light ~ To Test Data Lamp 0 Data Lamp 1 Data Lamp 2 Data Lamp 3 Data Lamp 4 Data Lamp 5 Data Lamp 6 Data Lamp 7 Input Address Memory Run Data Pushbutton 0 Data Pushbutton 1 Data Pushbutton 2 Data Pushbutton 3 Data Pushbutton 4 Data Pushbutton 5 Data Pushbutton 6 Data Pushbutton 7 Clear Display (Address) Read (Memory) Start PR-22 4/1/71 EXAMPLE OF CONSOLE USE Load the program (all octal numbers) LOOP OUTPUT- Location Contents Symbolic Instruction 003 004 005 006 007 010 Initial value of P Reg. ADD B C=l all 004 103 001 134 200 344 004 200 xxx STORE B JPD UNC OUTPUT LOOP Steps: 1. Power On 2. Start 3. Stop 4. Clear 5. Enter 003 6. Set (Address) 7. Clear 8. Enter 004 9. Store (Memory) 10. Clear 11. Enter 103 12 . Store 13 . Clear 14. Enter 001 15 Store 16 • Clear 17. Enter 134 IS . Store 19 Clear 20e Enter 200 21. Store 22. Clear 23. Enter 344 24. Store 25. Clear 26. Enter 004 27. Store 28. Display (Addres s) e II Step 2 7 concluded the entry process. Step 28 is a double check that the Address Register has the correct value which in this case should be 012 I the next address. To check the entry of the data, which is a good habit to get into, or in general, to examine memory proceed with 34. Read (should be 001) 35. Read (should be 134) 36. Read (should be 200) 37. Read (should be 344) 38. Read (should be 004) 29. Clear 30. Enter 003 31. Set (Addre s s) 32. Read (should be 004) 33. Read (should be 103) To run the program 39. Start This program adds 1 to the B Register I puts the value of B out to loc-ation 200 ' and hence the Data Lamps I and recycles or loops. The S binary counting process should be in evidence on the Data Lamps though the lamps will be operating too fast in the lower order positions to observe the action in detail. PR-23 4/1/71 SUMMARY OF INSTRUCTION CODING Instruction First Byte Octal Digits D-- Add, Sub, Load, Store -D- B Reg = X Reg = Or I And, Lneg Jumps o A Reg = 1 2 3 A Reg = B Reg = X Reg = Unc. = Bit Test and Manipulation Shifts, Rotates (one byte only) Miscellaneous (one byte only) Set to 0 = Set to 1 = Skip on 0 = Skip on 1 = 0 1 2 3 = o 1 2 3 Or = (Noop = And = Lneg = 0 1) 2 JPD = IFI= 4 5 6 7 JMD = JM! = 3 Constant = Memory = Indirect = Indexed = Ind/Ind = Constant = Memory = Indirect = Indexed = Ind/Ind = ( f 0) = ( = 0) = ( < 0) = ( ~ 0) = (> 0) = 3 4 5 6 7 3 4 5 6 7 3 4 5 6 7 o 1 2 Digit Value = Position 2 3 Right Shift = 0 Right Rotates = 1 Left Shift = 2 Left Rotate = 3 rHalt ~ ~~ ~oop= Add = Sub = Load = Store = --D A= 0 B= 4 ----plus---1 place = 1 2 places = 2 3 places = 3 4 places = 0 U[Any value] [ 1 o ] PR-24 4/1/71