Historical Document · 1964
Declassified NSA history: punched-card prehistory (750 machines by 1945), ATLAS I/II, ABEL, ABNER, BAKER, NOMAD, SOLO, BOGART, IBM 701–7090, HARVEST and TRACTOR, with a dated installation table (105 pp)
Doc ID: 6586784 .r ' HISTORY OF NSA GENERAL-PURPOSE ELECTRONIC DIGITAL COMPUTERS ~ -· . ·.~ •. 1964 pproved for Release by NSA on 2-09-2004, FOIA Case# 41023 • Doc ID: 6586784 HISTORY OF NSA GENERAL-PURPOSE ELECTRONIC DIGITAL COMPUTERS By Samuel S. Snyder • ' rI j 1964 .- ,_ Department of Defense Washington, D. c. 20301 -FOR OFFICIAL USE ONLY I. Doc ID: 6586784 r PREFACE r i T--·----- ! I i The author has attempted to write this material so that it will be easily understood by those who have had only limited experience with computers. To aid those readers, several terms and concepts have been defined, and Chapter 1 includes a brief discussion of principles of computer operation, programming, data-preparation problems, and automatic programming. Engineering terminology has been held to a minimum, and the history of programmer training, personnel and organizational growth, and-the like has not been treated. To some small extent, the comments on operational utility bring out the very real usefulness of computers for the solution of data-processing problems. The cutoff date for even'C!:f-related -her·e-·--·was-the end of December 1963. s.s.s. ii Doc ID: 6586784 TABLE OF CONTF.NTS CHAPTER 1 -- BACKGROUND Page ·Description Punched Card Equipment and the Computer Computers in NSA - - - - - - - - - Computer Principles - - - - - - - - - Programming Principles Data Preparation - - - - - - - - Automatic Programming - - - - - - - - - - - Special-Purpose Attachments - - - - Impact of NSA on Commercial Computer Developments CHAPTER 2 -- AGENCY-SPONSORED COMPUTERS ATLAS I and ABEL - - - - - - ATLAS II - - - - - - - - - - - - - ABNER and BAKER - - - - - - - - - - NOMAD - - - - - - - - - - - - SOLO - - - - - - BOGART - - - - - CUB - - - UNIVAC 1224A (CRISPI) - - - - - - - HARVEST - - - - - - - - - - HARVEST Modes of Operation - - - --Ar-i-thme.t-ic Mode -- - - - - - Streaming Mode - - - - Indexing and Setup - Streaming Instructions - - - Adjustments - - - - - - Special Memory Features - - - TRACTOR - - - - - - - - - HARVEST Operational System (HOPS) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8 - - 13 - - 14 .28 - - 29 - - 31 - - .36 - - .36 - - .39 46 - - A-6 ___ _ - - 55 - - 58 59 59 - - 59 60 .61 CHAPTER 3 -- COMMERCIAL COMPUTERS International Business Machines Corporation - ·6: IBM-701 - - - - - - - - - - - - - 65 IBM-7 0 2 - - - - - 66 IBM-705 - - - - ~6 IBM-704 - - - - - - - - 67 IBM-650 - - - - - - - - - - - - - 67 IBM-1401 - - - - - - - - - - - - - - 71 IBM-1410 - - - - - - - - - - - - - - 71 IBM-7090 - - - - - - - - - - - - - 76 iii oc ID: 6586784 TABLE OF CONTENTS (CONTINUED) Page Description General Precision, Inc. - - - - - - - LGP-30 - - - - - - - - - - - - - - Control Data Corporation - - CDC-1604 - - - - - - - - - - - - - CDC-160A - - - - - - - - - - - - 76 - - 76 78 - - 78 - - 82 CHAPTER 4 -- REMOTE-OPERATED COMPUTERS ROGUE (ALWAC IIIE) ROB ROY (BOGART) RYE (UNIVAC 490) - - - - 85 88 - - - - 89 APPENDIX Table 1. Chronological Listing - - - - - 2. ATLAS I Instruction Code - - - - 11 3. U.S. Electronic Computer Ac tivi ty II in 1947 - - - - - - - - - - - - 11 4 • ABNER Instruction Code - - References - - - - - - - - - - - - - - - 11 - - - 93 96 - - - 97 98 - - - 99 ------ fLLlfSTRATIONS Figure 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description Page Block Diagram of Digital Computer Typical Problem Flow Chart - - - ATLAS I Console - - - - - - - - - - ATLAS I Main Frame, with Input Tape Reader in Foreground,. Console in Back ABEL - - - - - - - - - - - - - - ATLAS II Main Frame (Partial View) - ATLAS II Console - - - - - - - - - - ATLAS II Input-Output - - - - - Mercury Delay Line (Diagrammatic) ABNER (1) Memory Cabinet - - - - - - ABNER (1) Console Panel - - - ABNER (2) Console - - - - - - ~.(2) Raytheon Tape Drives - - - ABNER (2) Main Frame - - - - - - iv ----- ---·- . vs ii@ £i 3 5 9 9 11 . - - 15 - - 15 16 18 20 - - 24 - - 25 25 - - 26 oc ID: 6586784 Illustrations (continued) Figure 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Description Page BAKER - - - - - - - - - - - - - - SOLO - - - - - - - - - - - - - BOGART Console, with IBM 727 Tape Drives BOGART, Serial 2 - - - - - - - - 26 32 34 35 CUB - - - - - - - - - - - - - - 37 Partial View of CRISPI, Showing Paper-Tape Input, UNIVAC 1224A, and "B" Console - 37 HARVEST System Block Diagram - - - - - - - 44 HARVEST Operator's Console, Showing IBM 1403 Line Printer, Right Background - - - 47 HARVEST Operating Area, General View, Showing TRACTOR in Left Background - - 48 HARVEST Maintenance and Engineering Consoles: Arithmetic and Logic Unit (left) Streaming Unit (right} - - - - - - 49 HARVEST -- The 16 Frames of the Central Processing Unit - - - - - - - - - - - - - 50 HARVEST Tape Control Units and Tape Drives 51 HARVEST -- The 6 Large Memories - - - - - 52 HARVEST -- One Unit of the Fast Memory - - 53 HARVEST -- TRACTOR Cartridge Handler - - - 54 HARVEST Streaming Data Paths - - - - - - - 56 IBM-705, Showing SINBAD Control Panel at Right of 705 Console - - - - - - 68 IBM-705 Core Memory - - - - - - - - 69 IBM-704 - - - - - - - - - - - - 70 IBM-704 Core-Memo-ry-------------- -- - - - - - - 70 IBM-650 General View - - - - - - - - 72 IBM-650 Console - - - - 72 IBM-650 Disk Storage - - - - - - - - 73 IBM-650 Inquiry Station - - - - 74 IBM-1401 - - - - - - - - - - 75 IBM-7090 Console - - 77 LGP-30 - - - - - - - - - - 79 WELCHER - - - - - - - - 80 CDC-1604 - - - - - - - - 81 Control Data 160-A Computer - 83 ALWAC IIIE - - - - - - 87 ROB ROY Outstation - - - - - 90 ROB ROY Control Panel - - - - - - - 90 UNIVAC 490 {RYE) General View - - - 91 v oc ID: 6586784 .•. ·!!~. .~ ~ · r-'r C~PTER 1 BACKGROUND Ji? . ~-·· :,T-· Most writers on digital computer development tend to start with discussions of the abacus and continue with Charles Babbage's Analytic Engine, the desk calculator, and the big relay calculators of Bell Laboratories and Harvard. Indeed, the development of computing machinery did follow such a path. But the role of computers at NSA can be better appreciated when considered from the viewpoint of application. Punched Card Equipment and the Computer The extraordinary versatility and efficiency of electronic computers have made them useful in handling almost every class of data-processing and analytic problem. From this point of view and in this respect, at NSA, punched-card equipment -keypunch, reproducer, sorter, collator, and tabulator -- could be called the forerunners of the electronic computer. For the 15 years beginning about 1935, NSA's predecessors used punched.-card equipment to attack wider and wider ranges of problems. During this time many special-purpose machines were also built, including some designed a~ attachments to punched-card equipment. The use of punched~card equipments as general-purpose tools continued to grow until, by the end of World War II, 750 machines had been installed. Punched-card equipment -- keypunch, reproducer, sorter, co-llator, and tabulator -- were the forerunr1er·s--0Ith·e--e1ectronic computer in every respect excepting speed and automatic operation. · This is true because of the use of the punched-card as a unit record, flexibility of plugboard together with switching capabilities in each machine, and versatility ~nherent in successive card passes through different equipments. The following types of data analyses could be done using punched-card equipments: expanding, reproducing (Reproducer) distributing, sorting (Sorter) merging, selecting (Collator) counting, printing (Tabulator) The general-purpose computer logically corresponds to punched-card equipment in that a variety of elementary operations (the order code) can be combined in a variety of ways I Doc ID: 6586784 (the programl) and applied to unit records (data stored in specific memory locations). The versatility is further increased by treating the program steps (instructions) as data themselves and eliminating the necessity for manual operations between successive logical operations. Finally, the great difference in speed made possible by electronic circuitry in the large computers has virtually elirilinated the punched-card approach as our principal general-purpose tool. Computers in NSA With the earliest design work on computers, in 1946, came the realization of the potential usefulness of such machines for Agency purposes. Quite probably this Agency's predecessors were the first to develop sophisticated analytic applications of such machines. This story is detailed later in the·discussions of ATLAS I and ABNER. The use of computers by NSA has increased considerably, ·beginning with one of the first machines in the country, installed in December 1950. NSA's computer installation probably ranks among the largest in the country. The chronological listing (Table 1, page 93) shows these acquisitions in the order of their installation and includes references to the page in the text where each computer is discussed. Computer Principles --· . . -.. Most modern electronic digital computers, begin:tiTiicf----·-·- - _____ _ wi-th the ·su:cc-essors to the famous ENIAC, have been composed of four principal units: input-output, storage, arithmetic, and control (fig. 1). Data and instructions, prepared in advance on some lt\achine-readable medium (punched cards, tape, and the like), are fed into the machine system, and the data is operated on automatically, according to the steps specified in the instructions. Such instructions are stored in the same internal storage medium as the problem data but are interpreted by the control unit. An "instruction" normally indicates: (1) the operation to be performed by the arithmetic unit, (2) the location in storage (its address) of one or more operands, and (3) the address of the result of the operation. One of the reasons for the great flexibility of the modern computer is its ability to modify its own instructions or the course of problem solution, depending upon intermediate results. A variation of this capability is the technique of causing the incoming data-stream characters themselves to form addresses for insertion in skeleton instructions later to be executed. . 2 -.. JR! P.'W.l L;:_ _r .... ,...i'••.A • -~~_,__.__ ..... .c.:-.... .}, . I Doc ID: 6586784 CONTROL / / JI. ··- -· --- / I I + '' ----- - ------- INPUTOUTPUT STORAGE ARITHMETIC - - - - Data Paths _ _ _ _ Control Paths Figure 1.-Block Diagram of Digital Computer 3 I r Doc ID: 6586784 i I l l I Programming Principles Any analytic or data-processing requirement, however complex, can be logically reduced to a succession of elementary operations that follow from binary decision-points (yesor-no choices}, provided knowledge exists of a logical method of attack. A flow chart (fig. 2) for a sample problem shows the use of such dichotomous, or two-choice, logic to break a complex problem into the major steps that will lead to possible solution. In similar fashion, each of such major steps is susceptible to further breakdown into smaller, more detailed, steps, and so on down to the individual elementary machine operations that are the smallest logical unit and that correspond to the individual computer instructions. Data Preparation An important and essential aspect of the use of any data processing machines is the initial step -- the preparation of data for input. In connection with the general-purpose use of punched-card equipment, the key-punch has been mentioned as providing means of transforming information into a form that can be read by other machines. The key-punch perforates cards in specific positions to represent data under study. Punched paper tape is also used as machine input and is usually punched in 5- or 7-level codes. Recently the use of magnetic tape has increased, although it must usually be prepared from punched- cards or--ta-pe-.---~ points should be emphasized: 1. Our method for going from hard copy to machine-readable mediums has not improved -- a small army of key-punchers and paper-tape punchers is still employed. 2. The existence of several media, here and in the field, requires the use of large quantities of equipment and time just to convert from one medium to another (frequently several times within one job)-. Many machines, including several general-purpose computers, have been built for the sole purpose of data conversion and rearrangement. Automatic Programming In the preceding.brief description of the principal parts of the typical computer arid of organizing a problem for computer attack, the necessity for a breakdown into elementary operations was pointed out. Most of these elementary operations are more detailed -- require much finer attention -- than people are accustomed to. When a workable program 4 L ·=· I ·.:Z'i o.up A ·1 Doc ID: 6586784 START---- READ IN (NEXT) TEXT EXAMINE (IDENTIFY) FIRST (NEXT) CHARACTER ADD "1" TO MEMORY CELL FOR THAT CHARACTER ADD "1" TO MEMORY CELL FOR TOTAL CHARACTERS NO YES SET UP AND EXECUTE PRINT ROUTINE- - rCLEAR CHARACTER COUNT CELLS AND TOTAL CELL NO YES STOP FIGURE 2. TYPICAL PROBLEM. FLOW CHART -.FREQUENCY DISTRIBUTION OF ALPHABETIC TEXT 5 Doc ID: 6586784 (or routine or subroutine, as smaller subdivisions are called) is completed, it is natural to try to avoid the necessity of repeating the whole. operation the next time this particular function is req~ired. As a result, routines of standard functions are commonly stored in "libraries," and special programs, called "compilers," perform the function of combining several such routines and adjusting addresses for varying conditions. To facilitate the writing of machine-language instructions, the instruction codes of .many computers use mnemonics that must later be converted into the individual computer words. Programs for performing this conversion automatically are called "assemblers." Higher forms of languages have been developed that use a combination of rigorous English and mathematical notation to express functions and parameters of problems and thus release the analyst/ programmer from becoming a full-time machine specialist. Programs for transforming these higher languages are called "translators:" they generate actual computer programs ready to execute a problem solution. Special programs for regulating overall computer operations, keeping records, monitoring various types of simultaneous operations, and for many other purposes are called "supervisors" or "executive" routines. In the past, programmers in NSA have been less inclined to use these techniques than computer users in other fields, primarily because commercially developed systems have been unsuited to the specialized nature of Agency operations. More recently, however, such techniques have become the rule, and the great ALPHA language-development effort required for HAR·-vEST-;-- for example, will certainly have -a:·- far-reaclifi1cj- -effect on future large systems. Special-Purpose Attachments In large-scale equipment planning, more and more use is being made of the combination of several kinds of equipment into single ·operating complexes. Actually, this procedure parallels what was done many years ago when attachments were built to function with the IBM Tabulator. In 1954 the FARMER proposal first suggested the idea of special attachments to a computer, and the design of HARVEST made specific provision for the attachment of external function devices. The currently popular application of this principle is the designing of highly efficient counting, comparing, or other processing devices for attachment to a general-purpose computer for use in sophisticated attacks on complicated problems to achieve greater efficiency than would be possible using the computer alone. Impact of NSA on Commercial Computer Developments In addition to contracts for computer purchase or lease and the development of engineering techniques, the primary ~· 6 D: 6586 8 influence of NSA on industry has been felt in those instances where technical leadership or management foresight has influenced or led directly to industrial computer pioneering. A few examples follow. First, the sponsorship of the ATLAS I by NSA's Navy predecessor led directly to placing Engineering Research Associates on a firm footing as one of the country's pioneering computer firms. ERA's commercial 1101 and 1103 computers were almost identical to ATLAS I and ATLAS II respectively. With the merger of ERA and the Eckert-Mauchly Corporation into the Remington-Rand-1JNIVAC organization, the 1101 and 1103 became a part of the UNIVAC line. Through the National Bureau of Standards, NSA's Army predecessor contracted for the construction of a 111ercury delay line memory for ABNER. The Technitrol Corporation not only built memories for ABNER and the National Bureau of Standards' SEAC, but later constructed the second ABNER and received a series of contracts for equipment using similar components. Technitrol went on to market a varied line of special and general-use equipment, much of it based on this experience. Another example is NSA's NOMAD contract with Raytheon Corporation. The NOMAD design was the direct forerunner of the Datama.tic ~1000, which was transformed into one of the early 10.achines in the Honeywell line. The realization, in 1955, that the transistor had a brJgll.t future .... -··-- - as an el.ectronic · component, led to this Agency's ·sponsorship of the construction by Philco Corporation of NSA's first practical, transistorized computer, SOLO. Marketed conunercially as the Transac S-1000, it became the world's first commercial transistorized computer. Beginning with the EDPM Type 701, the Agency-IBM experience is very impressive. Probably very few realize that IBM based much of its early computer philosophy upon NSA's experience with large data-processing problems. Certain features of the 704, representing improvements on the 701, resulted from sugges~ions by NSA personnel; similarly, the 702 was improved to become the 705. The PLANTATION (later RANCHO) study contract for HARVEST design, as well as NSA support for memory and magnetic tape researches, not only influenced IBM's 7030 (STRETCH) but also resulted in solving a number of fundamental logic and processing problems never before confronted in the computer field. Finally, the LIGHTNING researches into ultra-high-speed computer circuits and components -- work done under contract by IBM, RemingtonRand-UNIVAC, RCA, and others -- have undoubtedly had the greatest influence in the development of new computers and other digital equipment with basic operation times measured in nanoseconds (billionths of a second) . 7 jpfij gg; ·-"¥:..50.•·::'il~• 19w5. . rs1 l'Mi· ·t:& ~4·.*SQ@:#'.:-*MI.-~··.e .. - ... . . ·=:mm: ~ Doc ID: 6586784 CHAPTER 2 AGENCY-SPONSORED COMPUTERS In addition to operating an extensive computer installation, NSA has been a prime sponsor of computer developments. Of the nine electronic computer projects discussed in the following sections, two, ABNER and CUB, were designed and built by NSA (or predecessor) personnel. The rest were built under contract, following logical designs conceived or inspired by NSA personnel. A~LAS I and ABEL In the summer of 1946, Moore School of Electrical Engineering, University of Pennsylvania, sponsored a series of lectures on electronic computers. Among those who attended was LCDR James T. Pendergrass, a young mathematician at Navy's Communications Supplementary Activities, Washington (CSAW). As a result of hearing the computer proposals described at that time, LCDR Pendergrass prepared a report in which he proposed that the Navy acquire such a machine. His report included a general description of the proposed machine's logic, its code of instructions, and coded examples of typical problem solutions. The particular design advocated was of the· class known as one-address logic, and was based on the I.A.S. Computer then being developed at the Institute for Advanced Study, Princeton, New Jersey. CSAW went ahead with plans for construction of ATLAS I, and CSAW personnel perfected most of the basic algorithms, or .. a.eta-irea--m.ach-ine logic for executing each instruction. The contractor, Engineering Research Associates of St. Paul, Minnesota, used MIT's WHIRLWIND I logical design to a great extent. ATLAS I was delivered on 8 December 1950 and was running before Christmas. It employed parallel circuitry, contained approximately 2700 tubes, and cost about $950,000. Figures 3 and 4 show views of this machine. Although the original proposal had specified that !he ATLAS high-speed internal memory was to.utilize Selectron tubes, a decision was made to substitute a 16,384-word magnetic drum of a type similar to one already placed in operation by E.R.A. in other special-purpose equipment built for the Navy. Also, whereas I..CDR Pendergrass's proposal described a machine with 36-bit2 words (each word containing two one-address instructions), the ATLAS I design was finally based upon 24-bit 1 Selectron was the specially-designed electrostatic storage tube under development by Jan Rajchman at RCA's Princeton Laboratories. The development never achieved sufficient reliability for use as a practical computer memory. r 2 11 bit" -- binary digit ' ' 8 :; ) ,., Doc ID: 6586784 Figure 3 -ATLAS I Console Figure 4-ATLAS I Main Frame, with Input Tape Reader in Foreground, Console in Background 9 oc ID: 6586784 words {each with one single-address instruction). The drum memory was equipped with a flexible feature called "interlace," that permitted variations in address layout to be made for each program, using a plugboard setup. In effect, "lines" around the drum were renumbered by transposing certain bits of the address selection register in order to allow longer or shorter intervals between successive effective addresses, according to the particular needs of the program. Careful programming in conjunction with careful planning of the interlace plugging made it possible to attain extremely high speeds for given programs, compared to running time of programs written without attention to interlace. Thus, ac. cess timel could be reduced to 32 microseconds under the best conditions, compared with an average of 8,500 microseconds or a maximum of 17,000 microseconds. In May 1951, a modification, the "skip" feature, was introduced that added flexibility to programming by allowing the program address counter to advance by intervals greater than one {9, 17, 33, or 65). In effect, the operation of the interlace feature was made partly automatic. In June 1951, the installation of a "dial interlace" feature made selection of the interlace plugging simpler and eliminated the necessity of actually changing plugboards. Other features of ATLAS I's original design included logical multiply instruction, vector addition, several forms of ordinary arithmetic instructions, conditional jump instructions, and an elementary input-output procedure using punched paper tape. In 1952, an interesting new feature, the random jump instruction, was added. Employing a separate electronic attachment that supplied random bits of zero or one, this instruction made possible the generation of streams of random charac.:ters. The photoelectric tape-reading equipment-deli-- · vered with ATLAS I was found to be. quite slow (140 characters per second) compared with ATLAS I internal speeds; nor was it under program control. It was replaced by the newly developed Ferranti photoelectric tape reader that had a speed of 300 character$ ·per second. Table 2 contains the ATLAS I instruc-:tion reper.toire. Shortly after the completion of the ATLAS I design in 1949, a decision was made to construct a relay analog of the equipment, to assist in training programmers and to "debug" its programs (at least logically) before it was delivered. ABEL (fig. 5) was designed and constructed by CSAW personnel in about four months. Logically it was identical to ATLAS I, but its memory drum capacity was 2,047 words instead of 16,384, and its relay circuitry made it several hundred times slower. 1 access time -- time required to locate and read a word from memory into the arithmetic unit or vice-versa. 10 ,. ;~ ! I I • I F1gu~e 5 -- ABEL '• Doc ID: 6586784 After an initial period of perfecting operational and maintenance techniques, ABEL proved to be quite reliable. It was used not only for programmer training but also for generating various statistical tables. Principally because of the great difference in capacity of the memories of ATLAS I and ABEL, the latter could not be effectively used to debug large-scale ATLAS programs. After ATLAS I began operating at CSAW, ABEL was dismantled and transferred, through the Office of Naval Research, to the Navy Logistics Project at the George Washington University where it went back into service. After operation on the Navy Logistics Project for a time, it was presented to the George Washington University School of Engineering. Finally, in 1963, GWU presented ABEL to the Albert Einstein High School in Silver Spring, Maryland. Here upon advice of Agency representatives, it was dismantled for-the last time. Several months before the delivery of ATLAS I, an order was placed with ERA for the construction of another almost identical machine; it was delivered in May 1953. In 1956, both machines were modified by the addition of high-speed corel storage in the amount of 4,096 words. This addition modernized the machines and eased the programmers' burden; for before the addition of the high-speed magnetic-core memory, the extra effort required of programmers in putting instructions and constants in those locations in-the memory best adapted to maximmn use of the interlace feature was often excessive. In 1957, both ATLAS I's were moved to Fort Meade, and in November 1959 both machines were taken out of operation. ATLAS I, Serial 1, was salvaged, and the components used for other purposes;- -in--March 1960-; -·se-r-.ra.-i:- -2 was shipped to the Anti-Submarine Research Center, SACLANT, NATO Forces, at La Spezia, Italy. From a maintenance point of view, both machines performed extremely well. Although periods of down time for modifications and additions were necessary, the machines were usually operational above 90 percent in a reporting period. Many useful programs were written for ATLAS I, particularly for statistical and mathematical problems. Although the instructions were well-balanced for statistical and analytic uses, and the machines were designed and built for reliable operation, ATLAS I could not be used for problems demanding the handling of large volumes of data because of the lack of a magnetic-tape facility. 1 core -- also, rings or toroids, of magnetic ferrite material, strung at the junctions of intercrossing wires. Each core represents one bit of storage capacity. Thus, a 1,024word memory of 24-bit words would take the form of a stack of 24 matrices, _each matrix being a square array of cores, 32 cores to a side. 12 oc ID: 6586784 A'l'LAS II Seyeral months before ATLAS I was delivered, a new task was established that provided for the design of a successor. ATLAS II and ATLAS I differed in the following respects: 1. Storage -- Whereas ATLAS I had only drum storage, ATLAS II had, in addition, high-speed electrostatic storage for 1,024 words. 2. Word Size -- The word size on ATLAS II was 36 bits. ATLAS I word size was only 24 bits. 3. Instruction Logic -- ATLAS II used two-address instruction logic; ATLAS I, one-address. 4. Order Code -- Instruction sophistication was increased on ATLAS II. 5. Input-output -- ATLAS II had program-controlled input-output instructions. A lack of this capability was a serious drawback for ATLAS I. Two-address instruction logic was unique among computer projects. In some instructions, the two addresses .specified the locations of two operands; in other instructions, one of the addresses was an operand and the other a destination location. Among the more sophisticated new instructions were the repeat instruction (see ABNER, page l.4), s.everal modular-arithmetic instructions, a scale factor instruction, and an index jump instruction. ATLAS II was installed in October 1953. A second machine was also constructed,_ and it was-delivered in December 1954. The second ATLAS II differed from the first only in that it had a high-speed ferrite-core memory rather than an electrostatic tube memory. Originally the plan was to equip ATLAS II with Raytheon magnetic-tape drives using a data representation of one character per frame. However, a change was made to a conservative scheme for data representation involving two positions per information bit, resulting in three tape frames per character. Subsequently, this latter representation was felt to be too inefficient for most large problems. With the objective of achieving tape interchangeability and speeding up magnetic-tape operations, a red·esign effort was undertaken. However, this modification never reached operational effective- ness. Even though somewhat handicapped by lack of an effective maqnetic-tape system, both ATLAS II 1 s contributed considerably to the solution of many problems. Reliability was high for both machines, but Serial 1 required somewhat more. maintenance attention than Serial 2 because of the electrostatic tube storage. ATLAS I and ATLAS II were forerunners of the first two in a commercial line of Remington-Rand computers, the UNIVAC 1101 and 1103 respectively. Also, ATLAS II was the logical 13 Doc ID: 6586784 model for the first transistorized computer, SOLO {described on page 29}. ATLAS II, Serial 1, was taken out of operation in February 1960 and donated to the University of Texas; Serial 2 was turned over to the Second Army for disposal in May 1962. Figs. 6,· 7, and 8 show three views of ATLAS II. ABNER and BAKER In De~ember 1946, the first Pendergrass Report (see ATLAS I, page S} was received at the Army Security Agency, one of NSA's predecessor agencies. The potential value of electronic computers in ASA applications was recognized immediately, and plans were ma.de to consider the acquisition, by ASA, of a machine similar to Navy's proposed ATLAS. At that time, 1947, there ·were four main centers of electronic computer activity (see Table 3, page 97). During 1948, ASA analysts made visits to these installations, attended lectures at the Bureau of Standards' Digital Computer Laboratory, and performed progrannning experiments using ATLAS, UNIVAC, EDVAC, and RAYDAC order codes. The result of these investigations was a report favoring a design using four-address logic (RAYDAC or EDVAC) over the one-address logic (ATLAS or UNIVAC) . Four-address logic was favored for the following reasons: 1. Time estimates for executing representative operations showed higher speeds. ___ ·--- _··- _. 2. A- philosophic convfi:tion that the bulk of computer operations in ASA applications would be characterized by relatively simple operations on many data items rather than more complex operations upon data retained in the accumulator. In addition, UNIVAC was rejected for Agency use because it used decimal arithmetic internally and could only manipulate data as alphanumeric characters. Because of the many examples of Agency processes using binary notation, .a binary machine was felt to be a definite requirement. Based on the foregoing report recommendation, attempts were made to get estimates and commitments for building such a machine. The Raytheon Corporation was already committed to complete a first machine for Navy's Bureau of Aeronautics, and would not promise delivery of a second machine in less than three years. Moore School had undertaken to build EDVAC for Army Ordnance and could not consider offers for a possible second machine. In May 1948, Reeves Instrument Corporation announced that it was entering the digital computer field with REEVAC, a proposed machine based on EDVAC design. The basic EDVAC logic provided.for 45-bit words and a maximum of 16 four-· 14 ~ ·, ·: t Figure 6.-ATLAS II Main Frame {Partial View) - -·. Figure 7.-ATLAS II Console 15 >Jl£*1£AI• 1.-·:.-..- _44 Doc ID: 6586784 Figure 8.-ATLAS II Input-Output 16 Doc ID: 6586784 ,,._ address instructions. Its 1024-word memory was to be composed of mercury delay lines, with minimum access time being 48 microseconds and actual access varying between 48 and 384 microseconds. Dr. Samuel Lubkin, formerly at Moore School, headed the effort at Reeves. His proposed design contained several improvements upon the design of the EDVAC, and his price and promised date of delivery were attractive. But just as a contract with the Reeves Corporation was taking form, the company abandoned its plans to produce digital computers and released Dr. Lubkin to the staff of the National Bureau of Standards. Soon after, in August 1948, the Army Security Agency ~~4 the NBS concl~ded an agreement which provided that the Bu~eauwould produce a design for a computer that ASA engineers would build. NBS simultaneously would be designing and building a similar computer for themselves -- one of more modest capabilities. Also, NBS was to place the order for the mercury delay line memories for both machines. Shortly thereafter, several meetings were held to settle on the functional design of the ASA machine, and, to orient ASA engineers in their early design efforts, NBS engineers gave a series of lectures on digital computer logic. The proposed ASA machine was called ABNER. ABNER's mercury delay line memory was of particular interest. The acoustic delay line was developed around 1946 at the Moore School by Eckert, Sheppard, and Sharpless during planning for EDVAC. A succession of pulses (signal or no-signal) travels through an acoustic medium, say mercury, from one end to the other of a "delay line ... - --FTgure -9---s:hows a diagrammatic view of a mercury delay line. At the input end of the line is a crystal that converts an electrical pulse to a mechanical wave which travels through the mercury to the other end, where another crystal reconverts it to an electrical signal. The series of electrical signals is recirculated back to input, after pass·ing through detector, amplifier, and driver circuits to restore the shape and strength of the pulses. Also, in the part of the cycle external to the delay line are input and output circuits and "clock" pulses for synchronization. In mercury, the pulses travel at the speed of sound, which is much slower than the speed of electrical signals, and thus the delay in going from one end of the line to the other constitutes a form of storage. In ABNER, the mercury tank was a glass tube about two feet long; the delay time was 384 microseconds, or eight words of 48 bitsl at one-megacycle-per-second rate. Thus the 1,024 I The actual computer word length was 45 bits, allowing a 3-microsecond interval between words. ___;- Doc ID: 6586784 r r WORD CYCLE POSITIONS ~ -------~ 7 : 6 : 5 : 4 : 3 : 2 : 1 :0 CRYSTAL..J' DETECTOR DRIVER r CLOCK *""----~ l E ' - - t AMPLIFIER INPUT OUTPUT FIGURE 9. MERCURY DELAY LINE (DIAGRAMMATIC} r 18 c ID: 6586784 words were contained in two cabinets holding 64 mercury delay lines each. Figure 10 shows one side of one such cabinet, containing 32 tubes of mercury. (In the figure the actual glass tubes are not visible, being inside the metal cases shown in the upper part of the picture.) Because of the great variation between minimum access time and the maximum, efforts were made to minimize such delays. Mention has been made above of the improvements possible in ATLAS using ingenuity together with the interlace feature, when special care was taken in placement of words on the drum (page 10). In the case of ABNER, the savings by careful programming was not as great, but worth the effort. Referring to the diagram of Figure 9, a word at cycle position 0 would be immediately available for readout (access time: 48 microseconds), while a word at cycle position 7 would take 8 x 48, or 384 microseconds to be read (or written into). Therefore, instruction words and operands would be carefully placed at memory locations that would be immediately available, if possible, bearing in mind cycle positions (the actual memory address modulo 8) and the known execution times of instructions. For the next six or eight months, ASA engineers, working closely with several programmers, moved at full speed to perfect the engineering logic of the original set of instructions and devised several additional refinements. Also, primarily to acquire experience, they designed and built an input decimal_to-binary conversion device. About this time (July 1949-}---it-- --became apparent to ASA that NBS would not be able to complete the design of ABNER in a reasonable time, principally because of pressure to expedite completion of their own machine, SEAC. So the decision was made to go ahead and build ABNER without waiting for NBS. ASA engineers estimated that they could build the machine in two years. Meanwhile, the programmers, who had made programming experiments using the several available computer designs, became convinced that Agency operations justified flexibilities in data manipulation not available in these designs or in ABNER" as it was conceived at the time. They began work on a set of special computer instructions to be considered for inclusion in a future improved computer. Three principal classes of operations required special attention: character transformations, data-stream manipulations, and paired stream comparisons. These three lines of attention became interrelated and produced a combined solution that is quite interesting and historically significant. This result was possible because of the intimate working relationship between the programmers and engineers. 19 oc ID: 6586784 $ •••• I:> 1,$ • .. < ,,. .(') mii!!~-- •..@ .@ @ • • * 41· .,..., . ,, .............-; !'!J---..,. ., m;-.-: =~t::·:. -~ ~ ,$ $ ~ ; ....·- .$ ~ J/J .fit i j ~ "'t m--..- ... ,.._.:. .., J [z;+;*1 ·-:°) ~. #, ~"" • • •• •• . '•° •• • •• ••• •. ••• •••. ••• l/J .. i}J Ill -3 ·'1 $ a . • *• • @ .8 -~ @ -~ -~ ,f!l; .$ ti) 0 0 0 t:> i:> @ "' .... ••• .., .... . , ••• ••• ••• ••• •-••:: ..•••• ; ii- r Figure 10 -- ABNER Serial l Memory Cabinet 20 I . ' • ~ ~.;;;; ' """""""""' . ~ r • Doc ID: 6586784 r .. . ~·;-: ; :~<~~-~; These new features were incorporated in the lllachine under construction rather than waiting for a successor computer. The following describes briefly how the three requirements were implemented: 1.. Character transformations were treated in the computer as modular addition; that is, the corresponding alphanumeric characters of two words are summed, modulo n, where the value of n varies from 2 to 32. For situations dealing with character sets containing more than 32 characters, two addltional instructions were devised: one that dealt with two streams of 10-bit characters (four in each word) , and another in which the pairs of characters to be acted upon were within the same word . 2. Data stream manipulations originated as a requirement to transfer .groups of words among different portions of internal memory. The first version was thus a block ·transfer of a fixed number of words and was based upon a modification of the Shiftand-Extract instruction so as to repeat the instruction a fixed number of times. The capability of executing such an instruction any number of times came about with the development of the Halt feature. This feature originally was visualized as a means of automatically monitoring computer instruction executions so as to signal the completio